Lines Matching refs:readl
17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()
45 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
57 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_stop_tx()
64 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()
70 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
77 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()
95 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()
107 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()
119 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()
131 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()
144 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); in dwmac4_dma_interrupt()
145 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_interrupt()
206 u32 value = readl(ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac()
222 hi_addr = readl(ioaddr + high); in stmmac_dwmac4_get_mac_addr()
223 lo_addr = readl(ioaddr + low); in stmmac_dwmac4_get_mac_addr()