19 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_axi()
78 	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_dma_init_rx_chan()
96 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_dma_init_tx_chan()
117 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));  in dwmac4_dma_init_channel()
130 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_init()
153 		readl(ioaddr + DMA_CHAN_CONTROL(channel));  in _dwmac4_dump_dma_regs()
155 		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
157 		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
159 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
161 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
163 		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
165 		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
167 		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
169 		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
171 		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));  in _dwmac4_dump_dma_regs()
173 		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));  in _dwmac4_dump_dma_regs()
175 		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));  in _dwmac4_dump_dma_regs()
177 		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));  in _dwmac4_dump_dma_regs()
179 		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));  in _dwmac4_dump_dma_regs()
181 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
183 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
185 		readl(ioaddr + DMA_CHAN_STATUS(channel));  in _dwmac4_dump_dma_regs()
210 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_rx_chan_op_mode()
271 	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_rx_chan_op_mode()
279 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()
331 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);  in dwmac4_get_hw_feature()
356 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);  in dwmac4_get_hw_feature()
385 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);  in dwmac4_get_hw_feature()
403 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);  in dwmac4_get_hw_feature()
425 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
430 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
438 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()
451 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_set_bfsize()
461 	u32 value = readl(ioaddr + GMAC_EXT_CONFIG);  in dwmac4_enable_sph()
467 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));  in dwmac4_enable_sph()
477 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tbs()
486 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;  in dwmac4_enable_tbs()