1 // SPDX-License-Identifier: GPL-2.0-only
3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4  * DWC Ether MAC version 4.xx  has been used for  developing this code.
25 	if (axi->axi_lpi_en)  in dwmac4_dma_axi()
27 	if (axi->axi_xit_frm)  in dwmac4_dma_axi()
31 	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<  in dwmac4_dma_axi()
35 	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<  in dwmac4_dma_axi()
43 		switch (axi->axi_blen[i]) {  in dwmac4_dma_axi()
62 		case 4:  in dwmac4_dma_axi()
76 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;  in dwmac4_dma_init_rx_chan()
82 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))  in dwmac4_dma_init_rx_chan()
94 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;  in dwmac4_dma_init_tx_chan()
104 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))  in dwmac4_dma_init_tx_chan()
116 	/* common channel control register config */  in dwmac4_dma_init_channel()
118 	if (dma_cfg->pblx8)  in dwmac4_dma_init_channel()
133 	if (dma_cfg->fixed_burst)  in dwmac4_dma_init()
137 	if (dma_cfg->mixed_burst)  in dwmac4_dma_init()
140 	if (dma_cfg->aal)  in dwmac4_dma_init()
143 	if (dma_cfg->eame)  in dwmac4_dma_init()
149 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,  in _dwmac4_dump_dma_regs()  argument
152 	reg_space[DMA_CHAN_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
153 		readl(ioaddr + DMA_CHAN_CONTROL(channel));  in _dwmac4_dump_dma_regs()
154 	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
155 		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
156 	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
157 		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
158 	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
159 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
160 	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
161 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
162 	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
163 		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
164 	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
165 		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
166 	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =  in _dwmac4_dump_dma_regs()
167 		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
168 	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =  in _dwmac4_dump_dma_regs()
169 		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
170 	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =  in _dwmac4_dump_dma_regs()
171 		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));  in _dwmac4_dump_dma_regs()
172 	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =  in _dwmac4_dump_dma_regs()
173 		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));  in _dwmac4_dump_dma_regs()
174 	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =  in _dwmac4_dump_dma_regs()
175 		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));  in _dwmac4_dump_dma_regs()
176 	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =  in _dwmac4_dump_dma_regs()
177 		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));  in _dwmac4_dump_dma_regs()
178 	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =  in _dwmac4_dump_dma_regs()
179 		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));  in _dwmac4_dump_dma_regs()
180 	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
181 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
182 	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
183 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
184 	reg_space[DMA_CHAN_STATUS(channel) / 4] =  in _dwmac4_dump_dma_regs()
185 		readl(ioaddr + DMA_CHAN_STATUS(channel));  in _dwmac4_dump_dma_regs()
205 				       u32 channel, int fifosz, u8 qmode)  in dwmac4_dma_rx_chan_op_mode()  argument
207 	unsigned int rqs = fifosz / 256 - 1;  in dwmac4_dma_rx_chan_op_mode()
210 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_rx_chan_op_mode()
232 	/* Enable flow control only if each channel gets 4 KiB or more FIFO and  in dwmac4_dma_rx_chan_op_mode()
233 	 * only if channel is not an AVB channel.  in dwmac4_dma_rx_chan_op_mode()
251 			rfd = 0x03; /* Full-2.5K */  in dwmac4_dma_rx_chan_op_mode()
252 			rfa = 0x01; /* Full-1.5K */  in dwmac4_dma_rx_chan_op_mode()
256 			rfd = 0x07; /* Full-4.5K */  in dwmac4_dma_rx_chan_op_mode()
257 			rfa = 0x04; /* Full-3K */  in dwmac4_dma_rx_chan_op_mode()
268 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_rx_chan_op_mode()
271 	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_rx_chan_op_mode()
273 	       ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_rx_chan_op_mode()
277 				       u32 channel, int fifosz, u8 qmode)  in dwmac4_dma_tx_chan_op_mode()  argument
279 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()
280 	unsigned int tqs = fifosz / 256 - 1;  in dwmac4_dma_tx_chan_op_mode()
284 		/* Transmit COE type 2 cannot be done in cut-through mode. */  in dwmac4_dma_tx_chan_op_mode()
313 	 * TXQEN must be written for multi-channel operation and TQS must  in dwmac4_dma_tx_chan_op_mode()
325 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()
334 	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);  in dwmac4_get_hw_feature()
335 	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;  in dwmac4_get_hw_feature()
336 	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;  in dwmac4_get_hw_feature()
337 	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;  in dwmac4_get_hw_feature()
338 	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;  in dwmac4_get_hw_feature()
339 	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;  in dwmac4_get_hw_feature()
340 	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;  in dwmac4_get_hw_feature()
341 	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;  in dwmac4_get_hw_feature()
342 	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;  in dwmac4_get_hw_feature()
344 	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;  in dwmac4_get_hw_feature()
345 	/* IEEE 1588-2008 */  in dwmac4_get_hw_feature()
346 	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;  in dwmac4_get_hw_feature()
347 	/* 802.3az - Energy-Efficient Ethernet (EEE) */  in dwmac4_get_hw_feature()
348 	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;  in dwmac4_get_hw_feature()
350 	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;  in dwmac4_get_hw_feature()
351 	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;  in dwmac4_get_hw_feature()
352 	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;  in dwmac4_get_hw_feature()
353 	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;  in dwmac4_get_hw_feature()
357 	dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;  in dwmac4_get_hw_feature()
358 	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;  in dwmac4_get_hw_feature()
359 	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;  in dwmac4_get_hw_feature()
360 	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;  in dwmac4_get_hw_feature()
361 	dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;  in dwmac4_get_hw_feature()
363 	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;  in dwmac4_get_hw_feature()
364 	switch (dma_cap->addr64) {  in dwmac4_get_hw_feature()
366 		dma_cap->addr64 = 32;  in dwmac4_get_hw_feature()
369 		dma_cap->addr64 = 40;  in dwmac4_get_hw_feature()
372 		dma_cap->addr64 = 48;  in dwmac4_get_hw_feature()
375 		dma_cap->addr64 = 32;  in dwmac4_get_hw_feature()
382 	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);  in dwmac4_get_hw_feature()
383 	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);  in dwmac4_get_hw_feature()
387 	dma_cap->number_rx_channel =  in dwmac4_get_hw_feature()
389 	dma_cap->number_tx_channel =  in dwmac4_get_hw_feature()
392 	dma_cap->number_rx_queues =  in dwmac4_get_hw_feature()
394 	dma_cap->number_tx_queues =  in dwmac4_get_hw_feature()
397 	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;  in dwmac4_get_hw_feature()
399 	/* IEEE 1588-2002 */  in dwmac4_get_hw_feature()
400 	dma_cap->time_stamp = 0;  in dwmac4_get_hw_feature()
406 	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;  in dwmac4_get_hw_feature()
407 	dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;  in dwmac4_get_hw_feature()
408 	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;  in dwmac4_get_hw_feature()
409 	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;  in dwmac4_get_hw_feature()
410 	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;  in dwmac4_get_hw_feature()
411 	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;  in dwmac4_get_hw_feature()
412 	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;  in dwmac4_get_hw_feature()
413 	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;  in dwmac4_get_hw_feature()
414 	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;  in dwmac4_get_hw_feature()
415 	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;  in dwmac4_get_hw_feature()
436 static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)  in dwmac4_qmode()  argument
438 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()
446 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()
488 		return -EIO;  in dwmac4_enable_tbs()