Lines Matching +full:flow +full:- +full:control

1 /* SPDX-License-Identifier: GPL-2.0-only */
3   Copyright (C) 2007-2009  STMicroelectronics Ltd
20 #define GMAC_FLOW_CTRL		0x00000018	/* Flow Control */
23 #define GMAC_WAKEUP_FILTER	0x00000028	/* Wake-up Frame Filter */
47 /* PMT Control and Status */
61  * LPI status, timer and control register offset
66 /* LPI control and status defines */
119 #define GMAC_CONTROL_LM		0x00001000	/* Loop-back mode */
139 #define GMAC_FRAME_FILTER_PCF	0x00000080	/* Pass Control frames */
147 /* GMAC FLOW CTRL defines */
151 #define GMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */
152 #define GMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */
153 #define GMAC_FLOW_CTRL_FCB_BPA	0x00000001	/* Flow Control Busy ... */
177 #define GMAC_DEBUG_RXFSTS_MASK	GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
196 /*--- DMA BLOCK defines ---*/
214 #define DMA_BUS_MODE_RPBL_MASK	0x007e0000	/* Rx-Programmable Burst Len */
220 /* DMA CRS Control and Status Register Mapping */
265 /* Receive flow control activation field
266  * RFA field in DMA control register, bits 23,10:9
270 /* Receive flow control deactivation field
271  * RFD field in DMA control register, bits 22,12:11
278  *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
279  *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
280  *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
281  *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
282  *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
283  *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
284  *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
285  *   1,11 - Reserved
294  * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),