Lines Matching +full:ctrl +full:- +full:module
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
64 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
65 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; in socfpga_dwmac_fix_mac_speed()
66 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
67 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
69 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
97 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
102 struct device_node *np = dev->of_node; in socfpga_dwmac_parse_data()
113 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); in socfpga_dwmac_parse_data()
115 dev_info(dev, "No sysmgr-syscon node found\n"); in socfpga_dwmac_parse_data()
119 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); in socfpga_dwmac_parse_data()
121 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); in socfpga_dwmac_parse_data()
122 return -EINVAL; in socfpga_dwmac_parse_data()
125 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); in socfpga_dwmac_parse_data()
127 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); in socfpga_dwmac_parse_data()
128 return -EINVAL; in socfpga_dwmac_parse_data()
131 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); in socfpga_dwmac_parse_data()
133 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); in socfpga_dwmac_parse_data()
139 return -EINVAL; in socfpga_dwmac_parse_data()
142 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); in socfpga_dwmac_parse_data()
143 if (IS_ERR(dwmac->splitter_base)) { in socfpga_dwmac_parse_data()
145 return PTR_ERR(dwmac->splitter_base); in socfpga_dwmac_parse_data()
150 "altr,gmii-to-sgmii-converter", 0); in socfpga_dwmac_parse_data()
152 index = of_property_match_string(np_sgmii_adapter, "reg-names", in socfpga_dwmac_parse_data()
161 ret = -EINVAL; in socfpga_dwmac_parse_data()
165 dwmac->splitter_base = in socfpga_dwmac_parse_data()
168 if (IS_ERR(dwmac->splitter_base)) { in socfpga_dwmac_parse_data()
169 ret = PTR_ERR(dwmac->splitter_base); in socfpga_dwmac_parse_data()
174 index = of_property_match_string(np_sgmii_adapter, "reg-names", in socfpga_dwmac_parse_data()
183 ret = -EINVAL; in socfpga_dwmac_parse_data()
187 dwmac->pcs.sgmii_adapter_base = in socfpga_dwmac_parse_data()
190 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { in socfpga_dwmac_parse_data()
191 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); in socfpga_dwmac_parse_data()
196 index = of_property_match_string(np_sgmii_adapter, "reg-names", in socfpga_dwmac_parse_data()
205 ret = -EINVAL; in socfpga_dwmac_parse_data()
209 dwmac->pcs.tse_pcs_base = in socfpga_dwmac_parse_data()
212 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { in socfpga_dwmac_parse_data()
213 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); in socfpga_dwmac_parse_data()
218 dwmac->reg_offset = reg_offset; in socfpga_dwmac_parse_data()
219 dwmac->reg_shift = reg_shift; in socfpga_dwmac_parse_data()
220 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; in socfpga_dwmac_parse_data()
221 dwmac->dev = dev; in socfpga_dwmac_parse_data()
233 struct net_device *ndev = dev_get_drvdata(dwmac->dev); in socfpga_get_plat_phymode()
236 return priv->plat->interface; in socfpga_get_plat_phymode()
257 return -EINVAL; in socfpga_set_phy_mode_common()
264 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; in socfpga_gen5_set_phy_mode()
266 u32 reg_offset = dwmac->reg_offset; in socfpga_gen5_set_phy_mode()
267 u32 reg_shift = dwmac->reg_shift; in socfpga_gen5_set_phy_mode()
268 u32 ctrl, val, module; in socfpga_gen5_set_phy_mode() local
271 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); in socfpga_gen5_set_phy_mode()
272 return -EINVAL; in socfpga_gen5_set_phy_mode()
279 if (dwmac->splitter_base) in socfpga_gen5_set_phy_mode()
283 reset_control_assert(dwmac->stmmac_ocp_rst); in socfpga_gen5_set_phy_mode()
284 reset_control_assert(dwmac->stmmac_rst); in socfpga_gen5_set_phy_mode()
286 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); in socfpga_gen5_set_phy_mode()
287 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); in socfpga_gen5_set_phy_mode()
288 ctrl |= val << reg_shift; in socfpga_gen5_set_phy_mode()
290 if (dwmac->f2h_ptp_ref_clk || in socfpga_gen5_set_phy_mode()
295 &module); in socfpga_gen5_set_phy_mode()
296 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
298 module); in socfpga_gen5_set_phy_mode()
301 if (dwmac->f2h_ptp_ref_clk) in socfpga_gen5_set_phy_mode()
302 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); in socfpga_gen5_set_phy_mode()
304 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << in socfpga_gen5_set_phy_mode()
307 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); in socfpga_gen5_set_phy_mode()
312 reset_control_deassert(dwmac->stmmac_ocp_rst); in socfpga_gen5_set_phy_mode()
313 reset_control_deassert(dwmac->stmmac_rst); in socfpga_gen5_set_phy_mode()
315 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { in socfpga_gen5_set_phy_mode()
316 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); in socfpga_gen5_set_phy_mode()
317 return -EINVAL; in socfpga_gen5_set_phy_mode()
326 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; in socfpga_gen10_set_phy_mode()
328 u32 reg_offset = dwmac->reg_offset; in socfpga_gen10_set_phy_mode()
329 u32 reg_shift = dwmac->reg_shift; in socfpga_gen10_set_phy_mode()
330 u32 ctrl, val, module; in socfpga_gen10_set_phy_mode() local
333 return -EINVAL; in socfpga_gen10_set_phy_mode()
339 if (dwmac->splitter_base) in socfpga_gen10_set_phy_mode()
343 reset_control_assert(dwmac->stmmac_ocp_rst); in socfpga_gen10_set_phy_mode()
344 reset_control_assert(dwmac->stmmac_rst); in socfpga_gen10_set_phy_mode()
346 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); in socfpga_gen10_set_phy_mode()
347 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); in socfpga_gen10_set_phy_mode()
348 ctrl |= val; in socfpga_gen10_set_phy_mode()
350 if (dwmac->f2h_ptp_ref_clk || in socfpga_gen10_set_phy_mode()
354 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; in socfpga_gen10_set_phy_mode()
356 &module); in socfpga_gen10_set_phy_mode()
357 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift); in socfpga_gen10_set_phy_mode()
359 module); in socfpga_gen10_set_phy_mode()
361 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; in socfpga_gen10_set_phy_mode()
364 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); in socfpga_gen10_set_phy_mode()
369 reset_control_deassert(dwmac->stmmac_ocp_rst); in socfpga_gen10_set_phy_mode()
370 reset_control_deassert(dwmac->stmmac_rst); in socfpga_gen10_set_phy_mode()
372 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { in socfpga_gen10_set_phy_mode()
373 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); in socfpga_gen10_set_phy_mode()
374 return -EINVAL; in socfpga_gen10_set_phy_mode()
384 struct device *dev = &pdev->dev; in socfpga_dwmac_probe()
391 ops = device_get_match_data(&pdev->dev); in socfpga_dwmac_probe()
393 dev_err(&pdev->dev, "no of match data provided\n"); in socfpga_dwmac_probe()
394 return -EINVAL; in socfpga_dwmac_probe()
407 ret = -ENOMEM; in socfpga_dwmac_probe()
411 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp"); in socfpga_dwmac_probe()
412 if (IS_ERR(dwmac->stmmac_ocp_rst)) { in socfpga_dwmac_probe()
413 ret = PTR_ERR(dwmac->stmmac_ocp_rst); in socfpga_dwmac_probe()
418 reset_control_deassert(dwmac->stmmac_ocp_rst); in socfpga_dwmac_probe()
426 dwmac->ops = ops; in socfpga_dwmac_probe()
427 plat_dat->bsp_priv = dwmac; in socfpga_dwmac_probe()
428 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; in socfpga_dwmac_probe()
430 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in socfpga_dwmac_probe()
441 dwmac->stmmac_rst = stpriv->plat->stmmac_rst; in socfpga_dwmac_probe()
443 ret = ops->set_phy_mode(dwmac); in socfpga_dwmac_probe()
450 stmmac_dvr_remove(&pdev->dev); in socfpga_dwmac_probe()
464 dwmac_priv->ops->set_phy_mode(priv->plat->bsp_priv); in socfpga_dwmac_resume()
481 if (ndev->phydev) in socfpga_dwmac_resume()
482 phy_resume(ndev->phydev); in socfpga_dwmac_resume()
500 { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
501 { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
510 .name = "socfpga-dwmac",