1 // SPDX-License-Identifier: GPL-2.0
83 	int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;  in mt2712_set_interface()
84 	int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;  in mt2712_set_interface()
91 	 * configured, equals to (plat->variant->num_clks - 1) in default for all the case,  in mt2712_set_interface()
94 	plat->num_clks_to_config = plat->variant->num_clks - 1;  in mt2712_set_interface()
97 	switch (plat->phy_mode) {  in mt2712_set_interface()
102 		if (plat->rmii_clk_from_mac)  in mt2712_set_interface()
103 			plat->num_clks_to_config++;  in mt2712_set_interface()
113 		dev_err(plat->dev, "phy interface not supported\n");  in mt2712_set_interface()
114 		return -EINVAL;  in mt2712_set_interface()
117 	regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);  in mt2712_set_interface()
124 	struct mac_delay_struct *mac_delay = &plat->mac_delay;  in mt2712_delay_ps2stage()
126 	switch (plat->phy_mode) {  in mt2712_delay_ps2stage()
129 		/* 550ps per stage for MII/RMII */  in mt2712_delay_ps2stage()
130 		mac_delay->tx_delay /= 550;  in mt2712_delay_ps2stage()
131 		mac_delay->rx_delay /= 550;  in mt2712_delay_ps2stage()
137 		/* 170ps per stage for RGMII */  in mt2712_delay_ps2stage()
138 		mac_delay->tx_delay /= 170;  in mt2712_delay_ps2stage()
139 		mac_delay->rx_delay /= 170;  in mt2712_delay_ps2stage()
142 		dev_err(plat->dev, "phy interface not supported\n");  in mt2712_delay_ps2stage()
149 	struct mac_delay_struct *mac_delay = &plat->mac_delay;  in mt2712_delay_stage2ps()
151 	switch (plat->phy_mode) {  in mt2712_delay_stage2ps()
154 		/* 550ps per stage for MII/RMII */  in mt2712_delay_stage2ps()
155 		mac_delay->tx_delay *= 550;  in mt2712_delay_stage2ps()
156 		mac_delay->rx_delay *= 550;  in mt2712_delay_stage2ps()
162 		/* 170ps per stage for RGMII */  in mt2712_delay_stage2ps()
163 		mac_delay->tx_delay *= 170;  in mt2712_delay_stage2ps()
164 		mac_delay->rx_delay *= 170;  in mt2712_delay_stage2ps()
167 		dev_err(plat->dev, "phy interface not supported\n");  in mt2712_delay_stage2ps()
174 	struct mac_delay_struct *mac_delay = &plat->mac_delay;  in mt2712_set_delay()
179 	switch (plat->phy_mode) {  in mt2712_set_delay()
181 		delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);  in mt2712_set_delay()
182 		delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);  in mt2712_set_delay()
183 		delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);  in mt2712_set_delay()
185 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
186 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
187 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
190 		if (plat->rmii_clk_from_mac) {  in mt2712_set_delay()
193 			 * The egress timing can be adjusted by GTXC delay macro circuit.  in mt2712_set_delay()
194 			 * The ingress timing can be adjusted by TXC delay macro circuit.  in mt2712_set_delay()
196 			delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
197 			delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
198 			delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
200 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);  in mt2712_set_delay()
201 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);  in mt2712_set_delay()
202 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);  in mt2712_set_delay()
210 			if (plat->rmii_rxc) {  in mt2712_set_delay()
213 				 * by RXC delay macro circuit.  in mt2712_set_delay()
215 				delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
216 				delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
217 				delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
221 				 * by TXC delay macro circuit.  in mt2712_set_delay()
223 				delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
224 				delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
225 				delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
229 			 * and this bit is located in the same register with fine-tune  in mt2712_set_delay()
231 			if (mac_delay->tx_inv)  in mt2712_set_delay()
241 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);  in mt2712_set_delay()
242 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);  in mt2712_set_delay()
243 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);  in mt2712_set_delay()
245 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
246 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
247 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
250 		dev_err(plat->dev, "phy interface not supported\n");  in mt2712_set_delay()
251 		return -EINVAL;  in mt2712_set_delay()
253 	regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);  in mt2712_set_delay()
254 	regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);  in mt2712_set_delay()
273 	struct mac_delay_struct *mac_delay = &plat->mac_delay;  in mediatek_dwmac_config_dt()
277 	plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");  in mediatek_dwmac_config_dt()
278 	if (IS_ERR(plat->peri_regmap)) {  in mediatek_dwmac_config_dt()
279 		dev_err(plat->dev, "Failed to get pericfg syscon\n");  in mediatek_dwmac_config_dt()
280 		return PTR_ERR(plat->peri_regmap);  in mediatek_dwmac_config_dt()
283 	err = of_get_phy_mode(plat->np, &plat->phy_mode);  in mediatek_dwmac_config_dt()
285 		dev_err(plat->dev, "not find phy-mode\n");  in mediatek_dwmac_config_dt()
289 	if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {  in mediatek_dwmac_config_dt()
290 		if (tx_delay_ps < plat->variant->tx_delay_max) {  in mediatek_dwmac_config_dt()
291 			mac_delay->tx_delay = tx_delay_ps;  in mediatek_dwmac_config_dt()
293 			dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);  in mediatek_dwmac_config_dt()
294 			return -EINVAL;  in mediatek_dwmac_config_dt()
298 	if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {  in mediatek_dwmac_config_dt()
299 		if (rx_delay_ps < plat->variant->rx_delay_max) {  in mediatek_dwmac_config_dt()
300 			mac_delay->rx_delay = rx_delay_ps;  in mediatek_dwmac_config_dt()
302 			dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);  in mediatek_dwmac_config_dt()
303 			return -EINVAL;  in mediatek_dwmac_config_dt()
307 	mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");  in mediatek_dwmac_config_dt()
308 	mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");  in mediatek_dwmac_config_dt()
309 	plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");  in mediatek_dwmac_config_dt()
310 	plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");  in mediatek_dwmac_config_dt()
317 	const struct mediatek_dwmac_variant *variant = plat->variant;  in mediatek_dwmac_clk_init()
318 	int i, num = variant->num_clks;  in mediatek_dwmac_clk_init()
320 	plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL);  in mediatek_dwmac_clk_init()
321 	if (!plat->clks)  in mediatek_dwmac_clk_init()
322 		return -ENOMEM;  in mediatek_dwmac_clk_init()
325 		plat->clks[i].id = variant->clk_list[i];  in mediatek_dwmac_clk_init()
327 	plat->num_clks_to_config = variant->num_clks;  in mediatek_dwmac_clk_init()
329 	return devm_clk_bulk_get(plat->dev, num, plat->clks);  in mediatek_dwmac_clk_init()
335 	const struct mediatek_dwmac_variant *variant = plat->variant;  in mediatek_dwmac_init()
338 	ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask));  in mediatek_dwmac_init()
340 		dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret);  in mediatek_dwmac_init()
344 	ret = variant->dwmac_set_phy_interface(plat);  in mediatek_dwmac_init()
346 		dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);  in mediatek_dwmac_init()
350 	ret = variant->dwmac_set_delay(plat);  in mediatek_dwmac_init()
352 		dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);  in mediatek_dwmac_init()
356 	ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks);  in mediatek_dwmac_init()
358 		dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);  in mediatek_dwmac_init()
362 	pm_runtime_enable(&pdev->dev);  in mediatek_dwmac_init()
363 	pm_runtime_get_sync(&pdev->dev);  in mediatek_dwmac_init()
372 	clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks);  in mediatek_dwmac_exit()
374 	pm_runtime_put_sync(&pdev->dev);  in mediatek_dwmac_exit()
375 	pm_runtime_disable(&pdev->dev);  in mediatek_dwmac_exit()
385 	priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);  in mediatek_dwmac_probe()
387 		return -ENOMEM;  in mediatek_dwmac_probe()
389 	priv_plat->variant = of_device_get_match_data(&pdev->dev);  in mediatek_dwmac_probe()
390 	if (!priv_plat->variant) {  in mediatek_dwmac_probe()
391 		dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n");  in mediatek_dwmac_probe()
392 		return -EINVAL;  in mediatek_dwmac_probe()
395 	priv_plat->dev = &pdev->dev;  in mediatek_dwmac_probe()
396 	priv_plat->np = pdev->dev.of_node;  in mediatek_dwmac_probe()
414 	plat_dat->interface = priv_plat->phy_mode;  in mediatek_dwmac_probe()
415 	plat_dat->has_gmac4 = 1;  in mediatek_dwmac_probe()
416 	plat_dat->has_gmac = 0;  in mediatek_dwmac_probe()
417 	plat_dat->pmt = 0;  in mediatek_dwmac_probe()
418 	plat_dat->riwt_off = 1;  in mediatek_dwmac_probe()
419 	plat_dat->maxmtu = ETH_DATA_LEN;  in mediatek_dwmac_probe()
420 	plat_dat->bsp_priv = priv_plat;  in mediatek_dwmac_probe()
421 	plat_dat->init = mediatek_dwmac_init;  in mediatek_dwmac_probe()
422 	plat_dat->exit = mediatek_dwmac_exit;  in mediatek_dwmac_probe()
425 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);  in mediatek_dwmac_probe()
435 	{ .compatible = "mediatek,mt2712-gmac",
446 		.name           = "dwmac-mediatek",