Lines Matching refs:tx_queues_cfg
226 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
259 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
262 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
270 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
271 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
272 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
273 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
274 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
275 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
276 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
277 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()