Lines Matching refs:RTL_W32
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) macro
798 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); in r8168_phy_ocp_write()
808 RTL_W32(tp, GPHY_OCP, reg << 15); in r8168_phy_ocp_read()
819 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); in r8168_mac_ocp_write()
827 RTL_W32(tp, OCPDR, reg << 15); in r8168_mac_ocp_read()
886 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
900 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
921 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); in r8168dp_1_mdio_access()
922 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); in r8168dp_1_mdio_access()
923 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_access()
939 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); in r8168dp_1_mdio_read()
940 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_read()
950 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
955 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1025 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | in rtl_ephy_write()
1035 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); in rtl_ephy_read()
1059 RTL_W32(tp, ERIDR, val); in _rtl_eri_write()
1061 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_write()
1077 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_read()
1107 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1120 RTL_W32(tp, OCPDR, data); in r8168dp_ocp_write()
1121 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1275 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); in rtl8168d_efuse_read()
1292 RTL_W32(tp, IntrStatus_8125, bits); in rtl_ack_events()
1300 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1308 RTL_W32(tp, IntrMask_8125, tp->irq_mask); in rtl_irq_enable()
1495 RTL_W32(tp, RxConfig, rx_config); in rtl_set_rx_config_features()
1585 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); in rtl8169_do_counters()
1588 RTL_W32(tp, CounterAddrLow, cmd); in rtl8169_do_counters()
1589 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); in rtl8169_do_counters()
2185 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); in rtl_rar_set()
2188 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); in rtl_rar_set()
2222 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | in rtl_wol_suspend_quirk()
2304 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); in rtl_init_rxcfg()
2309 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2312 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); in rtl_init_rxcfg()
2315 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); in rtl_init_rxcfg()
2318 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2459 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); in rtl_rx_close()
2505 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_enable_rxdvgate()
2518 RTL_W32(tp, TxConfig, val); in rtl_set_tx_config_registers()
2534 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2535 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2536 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2537 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2554 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2589 RTL_W32(tp, MAR0 + 4, mc_filter[1]); in rtl_set_rx_mode()
2590 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2593 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); in rtl_set_rx_mode()
2605 RTL_W32(tp, CSIDR, value); in rtl_csi_write()
2606 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | in rtl_csi_write()
2616 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | in rtl_csi_read()
2856 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
2857 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
2892 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
2915 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
2967 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168g()
3207 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168h_1()
3260 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168ep()
3363 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8117()
3474 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3477 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3503 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3526 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3528 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
3605 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8125_common()
3760 RTL_W32(tp, i, 0); in rtl_hw_start_8125()