Lines Matching refs:ATTENTION_SINGLE
59 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) macro
60 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
561 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
562 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
563 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
564 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
578 {"PGLUE config_space", ATTENTION_SINGLE,
580 {"PGLUE misc_flr", ATTENTION_SINGLE,
584 {"PGLUE misc_mctp", ATTENTION_SINGLE,
586 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
587 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
588 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
606 {"General Attention 32", ATTENTION_SINGLE |
612 {"General Attention 35", ATTENTION_SINGLE |
620 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
628 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
631 {"MCP CPU", ATTENTION_SINGLE,
633 {"MCP Watchdog timer", ATTENTION_SINGLE,
635 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
636 {"AVS stop status ready", ATTENTION_SINGLE,
711 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
741 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
743 {"PERST_B assertion", ATTENTION_SINGLE,
745 {"PERST_B deassertion", ATTENTION_SINGLE,
756 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,