Lines Matching +full:0 +full:x33000000
130 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
132 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
162 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
164 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
166 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
285 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
287 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
289 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
291 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
293 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
295 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
297 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
299 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
301 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
303 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
305 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
307 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
309 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
320 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
321 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
322 #define CORE_TX_BD_TX_DST_MASK 0x3
400 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
401 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
402 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
404 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
406 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
410 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
412 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
419 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
421 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
423 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
425 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
427 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
429 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
431 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
434 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
435 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
436 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
438 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
445 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
447 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
454 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
456 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
470 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
474 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
476 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
479 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
480 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
481 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
483 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
485 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
487 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
509 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
519 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
524 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
526 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
528 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
530 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
532 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
536 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
538 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
543 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
545 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
547 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
549 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
551 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
553 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
558 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
560 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
562 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
564 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
566 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
568 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
570 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
579 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
581 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
583 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
592 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
594 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
596 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
604 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
663 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
664 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
665 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
667 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
675 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
678 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
680 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
682 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
689 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
691 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
698 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
700 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
723 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
726 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
728 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
730 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
767 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
768 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
769 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
771 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
773 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
775 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
778 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
779 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
780 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
782 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
784 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
787 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
788 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
789 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
791 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
793 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
795 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
797 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
799 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
801 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
804 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
806 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
808 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
1002 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1003 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1004 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1234 ETH_VER_KEY = 0,
1334 TUNNEL_CLSS_MAC_VLAN = 0,
1417 #define DMAE_CMD_SRC_MASK 0x1
1418 #define DMAE_CMD_SRC_SHIFT 0
1419 #define DMAE_CMD_DST_MASK 0x3
1421 #define DMAE_CMD_C_DST_MASK 0x1
1423 #define DMAE_CMD_CRC_RESET_MASK 0x1
1425 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1427 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1429 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1431 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1433 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1435 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1437 #define DMAE_CMD_RESERVED1_MASK 0x1
1439 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1441 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1443 #define DMAE_CMD_PORT_ID_MASK 0x3
1445 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1447 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1449 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1451 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1453 #define DMAE_CMD_RESERVED2_MASK 0x3
1461 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1462 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1463 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1474 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1475 #define DMAE_CMD_ERROR_BIT_SHIFT 0
1476 #define DMAE_CMD_RESERVED_MASK 0x7FFF
1531 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1532 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1533 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1535 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1537 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1539 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1542 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1543 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1544 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1546 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1548 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1550 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1552 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1554 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1556 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1568 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1569 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1570 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1572 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1574 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1576 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1579 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1580 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1581 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1583 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1585 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1587 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1589 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1591 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1593 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1618 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1619 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1620 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1622 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1624 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1626 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1628 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1630 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1632 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1646 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1647 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1648 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1650 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1652 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1667 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1668 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1669 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1671 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1678 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1679 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1680 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1682 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1684 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1686 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1688 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1697 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1698 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1699 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1701 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1703 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1709 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1710 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1711 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1713 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1715 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1717 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1719 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1721 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1736 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1737 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1738 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1740 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1742 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1744 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1746 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1748 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1750 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1757 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1758 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1759 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1761 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1763 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1765 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1767 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1769 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1771 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1773 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1775 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1782 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
1783 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
1784 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
1786 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
1788 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
1790 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
1792 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
1794 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
1801 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1802 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1803 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1805 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1812 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1813 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1814 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1816 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1961 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1962 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1963 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1985 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1986 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
1987 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1999 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
2000 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
2001 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
2010 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
2011 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
2012 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
2021 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
2022 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
2023 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
2045 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1
2046 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0
2047 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1
2049 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1
2051 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1
2053 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1
2055 #define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7
2087 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
2088 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
2089 #define DBG_BUS_LINE_IS_256B_MASK 0x1
2091 #define DBG_BUS_LINE_RESERVED_MASK 0x7
2106 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
2107 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
2108 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
2111 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
2112 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
2113 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
2115 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F
2122 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
2123 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
2124 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
2126 #define DBG_DUMP_REG_LENGTH_MASK 0xFF
2133 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
2134 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
2135 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
2148 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
2149 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
2150 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
2152 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
2162 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
2163 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
2164 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
2166 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
2191 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
2192 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2193 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
2219 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2220 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2221 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2239 #define DBG_RESET_REG_ADDR_MASK 0xFFFFFF
2240 #define DBG_RESET_REG_ADDR_SHIFT 0
2241 #define DBG_RESET_REG_IS_REMOVED_MASK 0x1
2243 #define DBG_RESET_REG_RESERVED_MASK 0x7F
2257 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1
2258 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
2259 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F
2684 #define ANY_PHASE_ID 0xffff
2788 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2789 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2790 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2797 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2798 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2799 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2806 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2807 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2808 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2815 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2816 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2817 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2824 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2825 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2826 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2828 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2851 #define INIT_CALLBACK_OP_OP_MASK 0xF
2852 #define INIT_CALLBACK_OP_OP_SHIFT 0
2853 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2862 #define INIT_DELAY_OP_OP_MASK 0xF
2863 #define INIT_DELAY_OP_OP_SHIFT 0
2864 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2872 #define INIT_IF_MODE_OP_OP_MASK 0xF
2873 #define INIT_IF_MODE_OP_OP_SHIFT 0
2874 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2876 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2885 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2886 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2887 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2889 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2892 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2893 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2894 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2896 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2911 #define INIT_RAW_OP_OP_MASK 0xF
2912 #define INIT_RAW_OP_OP_SHIFT 0
2913 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2935 #define INIT_WRITE_OP_OP_MASK 0xF
2936 #define INIT_WRITE_OP_OP_SHIFT 0
2937 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2939 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2941 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2943 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2951 #define INIT_READ_OP_OP_MASK 0xF
2952 #define INIT_READ_OP_OP_SHIFT 0
2953 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2955 #define INIT_READ_OP_RESERVED_MASK 0x1
2957 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
3384 #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff
3385 #define MCP_TRACE_FORMAT_MODULE_OFFSET 0
3386 #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
3388 #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000
3390 #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000
3392 #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000
3394 #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000
3712 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3715 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
3718 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
3721 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3724 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
3727 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
3730 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
3733 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
3736 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
3739 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
3742 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
3745 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
3809 * @return 0 on success, -1 on error.
3822 * @return 0 on success, -1 on error.
3837 * @return 0 on success, -1 on error.
3852 * @return 0 on success, -1 on error.
3995 * @brief qed_memset_session_ctx - Memset session context to 0 while
4006 * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4067 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
4068 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
4395 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
4835 #define DMAE_READY_CB 0
4856 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4857 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4858 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4860 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4862 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4864 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4866 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4868 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4870 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4873 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4874 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4875 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4877 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4879 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4881 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4883 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4885 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4887 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4890 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4891 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4892 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4894 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4896 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4899 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4900 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4901 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4903 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4905 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4908 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4909 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4910 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4912 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4914 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4917 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4918 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4919 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4921 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4923 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4926 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4927 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4928 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4930 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4932 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4935 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4936 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4937 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4939 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4941 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4943 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4946 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4947 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4948 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4950 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4952 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4954 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4956 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4958 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4960 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4963 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4964 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4965 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4967 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4969 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4971 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4973 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4975 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4977 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4980 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4981 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4982 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4984 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4986 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4988 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4990 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4992 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4994 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4997 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4998 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4999 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
5001 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5003 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5005 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5007 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5009 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5011 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
5014 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
5015 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
5016 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
5018 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5020 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5022 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
5024 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
5026 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
5028 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
5031 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
5032 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
5033 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
5035 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5037 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5039 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5041 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5043 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5045 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5048 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5049 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5050 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5052 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5054 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5056 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5058 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5060 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5124 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5125 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5126 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5128 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5130 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
5132 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5135 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5136 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
5137 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
5139 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5141 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5143 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5145 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5147 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5149 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5168 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5169 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5170 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5172 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
5174 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
5176 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
5178 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
5180 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5183 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5184 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
5185 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5187 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5189 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
5192 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
5193 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
5194 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
5196 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
5198 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
5201 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
5202 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
5203 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
5205 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5207 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5209 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5211 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5214 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
5215 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
5216 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
5218 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
5220 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
5222 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
5224 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
5226 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
5228 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5231 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5232 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5233 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5235 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5237 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5239 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5241 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
5243 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5245 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5272 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5273 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5274 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5276 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
5278 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
5280 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5283 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5284 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
5285 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
5287 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
5289 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5292 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
5293 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
5294 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
5296 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5298 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5300 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
5302 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
5304 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5306 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5309 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5310 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5311 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5313 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5315 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5317 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5319 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5321 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5323 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5364 ETH_OK = 0x00,
5527 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
5528 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5529 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
5531 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
5553 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
5554 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
5555 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
5557 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
5559 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
5561 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
5563 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
5565 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5567 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
5569 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
5576 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
5577 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
5578 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
5580 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
5582 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
5584 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
5586 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
5588 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
5590 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
5614 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
5615 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
5616 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5618 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
5620 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
5622 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5624 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5626 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
5628 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
5655 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
5656 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
5657 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5659 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
5661 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5663 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5665 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
5810 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
5811 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
5812 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
5814 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
5816 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
5818 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
5820 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
5970 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5971 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5972 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5974 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5976 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5978 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5980 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5982 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5984 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5987 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5988 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5989 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5991 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5993 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5995 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
5997 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
5999 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
6001 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
6004 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6005 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6006 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6008 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6010 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6013 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6014 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6015 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6017 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6019 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
6022 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6023 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6024 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6026 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6028 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6031 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6032 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6033 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6035 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6037 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6040 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
6041 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
6042 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
6044 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
6046 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
6049 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
6050 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
6051 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
6053 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6055 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6057 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6060 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6061 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6062 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6064 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6066 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6068 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6070 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
6072 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6074 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6077 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6081 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6083 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6085 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6087 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6089 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
6091 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
6094 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
6098 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
6100 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
6102 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6104 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
6106 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
6108 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
6111 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
6112 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
6115 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
6117 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6119 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6121 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6123 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6125 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6132 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6138 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6142 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6149 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6159 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
6166 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
6168 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
6199 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6200 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6201 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
6203 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
6205 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
6207 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
6210 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
6211 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
6212 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
6214 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
6216 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
6218 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
6220 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
6222 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
6224 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
6236 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6237 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6238 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
6240 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
6242 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6244 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
6246 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
6248 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
6250 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
6253 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
6254 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
6255 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
6257 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
6259 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
6261 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
6263 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
6265 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
6267 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
6270 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
6271 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
6272 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
6274 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
6276 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
6279 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
6280 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
6281 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
6283 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
6285 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
6288 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
6289 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
6290 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
6292 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
6294 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
6297 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
6298 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
6299 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
6301 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
6303 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
6306 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
6307 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
6308 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
6310 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
6312 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
6315 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
6316 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
6317 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
6319 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6321 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
6323 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
6326 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
6327 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
6328 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
6330 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
6332 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
6334 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
6336 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
6338 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
6340 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
6343 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
6347 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
6349 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
6351 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
6353 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
6355 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
6357 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
6360 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
6364 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
6366 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
6368 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6370 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
6372 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
6374 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
6377 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
6378 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
6381 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
6383 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
6385 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
6387 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
6389 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6391 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
6398 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
6404 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
6408 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
6415 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6425 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
6432 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
6434 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
6455 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
6456 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
6457 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
6459 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
6461 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
6463 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
6465 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
6467 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
6469 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
6471 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
6473 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
6475 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
6477 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
6484 GFT_PROFILE_IPV4 = 0,
6492 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6493 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6494 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6496 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6498 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6500 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6502 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6508 GFT_PROFILE_NO_TUNNEL = 0,
6519 GFT_PROFILE_ROCE_PROTOCOL = 0,
6541 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
6542 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
6543 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
6545 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
6547 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
6549 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
6551 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
6553 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
6555 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
6557 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
6559 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
6561 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
6563 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
6565 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
6567 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
6569 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
6571 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
6573 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
6575 #define GFT_RAM_LINE_TTL_MASK 0x1
6577 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
6579 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
6581 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
6583 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
6585 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
6587 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
6589 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
6591 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
6593 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
6595 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
6597 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
6599 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
6601 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
6604 #define GFT_RAM_LINE_DSCP_MASK 0x1
6605 #define GFT_RAM_LINE_DSCP_SHIFT 0
6606 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
6608 #define GFT_RAM_LINE_DST_IP_MASK 0x1
6610 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
6612 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
6614 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
6616 #define GFT_RAM_LINE_VLAN_MASK 0x1
6618 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
6620 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
6622 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
6624 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
6630 INNER_PROVIDER_VLAN = 0,
6647 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6648 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6649 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6651 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6653 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6655 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
6658 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6659 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6660 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6662 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6664 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6666 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6669 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6670 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6671 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6673 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6675 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6677 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6679 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6681 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6683 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6703 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6704 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6705 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6707 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6709 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6711 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
6714 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6715 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6716 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6718 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6720 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6722 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6725 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6726 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6727 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6729 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6731 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6733 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6735 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6737 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6739 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6769 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6770 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6771 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6773 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6775 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6778 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6779 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6780 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6782 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
6784 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6787 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6788 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6789 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6791 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6793 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
6795 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6797 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6799 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6801 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6804 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
6805 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
6806 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6808 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
6810 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6812 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6876 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6877 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6878 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
6918 RDMA_RETURN_OK = 0,
6968 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6969 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6970 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6972 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6974 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6976 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6978 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6980 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6982 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6984 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6986 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6988 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6991 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6992 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6993 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6996 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6997 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6998 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
7000 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
7026 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
7027 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
7028 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
7030 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7032 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
7051 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
7052 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
7053 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7055 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
7100 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
7101 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
7102 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
7104 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7106 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
7108 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
7111 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
7112 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
7113 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
7115 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7117 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7119 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
7122 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
7123 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
7124 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
7126 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
7128 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
7131 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
7132 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
7133 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7135 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7137 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
7139 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
7141 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
7143 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
7146 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
7147 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
7148 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
7150 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7152 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7154 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7156 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7158 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7160 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7178 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7179 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7180 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
7182 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7184 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7186 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7189 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7190 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7191 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7193 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7195 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7198 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7199 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7200 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7202 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7204 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7206 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7208 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7210 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7212 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7215 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7216 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7217 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7219 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7221 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7223 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7225 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7227 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7229 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7247 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7248 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7249 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7251 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7253 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7255 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7257 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7259 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
7261 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
7264 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
7265 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
7266 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
7268 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
7270 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
7272 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7274 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
7276 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
7278 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7281 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7282 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
7283 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7285 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7287 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
7290 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
7291 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
7292 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7294 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7296 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7299 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7300 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
7301 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7303 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7305 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
7308 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
7309 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
7310 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
7312 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
7314 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
7317 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
7318 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
7319 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
7321 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
7323 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
7326 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
7327 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
7328 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
7330 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7332 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7334 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7337 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7338 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
7339 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
7341 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
7343 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7345 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7347 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7349 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7351 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7354 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7355 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
7356 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
7358 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
7360 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
7362 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
7364 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
7366 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
7368 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
7371 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
7372 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
7373 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
7375 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
7377 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
7379 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7381 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
7383 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7385 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7388 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7389 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
7390 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7392 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7394 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7396 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7398 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7400 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7402 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
7405 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
7406 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
7409 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7411 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7413 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
7415 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
7417 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
7419 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
7422 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
7424 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
7426 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7428 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7430 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7432 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7434 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7436 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7439 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
7443 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7445 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
7447 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7449 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
7476 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7477 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7478 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7480 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7482 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
7484 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7486 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7488 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7491 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7492 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7493 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7495 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7497 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7500 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7501 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
7502 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7504 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
7506 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7509 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7510 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
7511 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7513 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7515 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7517 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7519 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7522 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7523 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7524 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7526 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7528 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
7530 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7532 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7534 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7536 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7539 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7540 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
7541 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7543 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7545 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7547 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7549 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7551 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7553 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
7637 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7638 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7639 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
7641 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
7643 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7645 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
7647 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7649 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7679 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
7680 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
7681 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7683 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F
7694 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7695 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7696 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7698 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7700 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7702 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7704 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7706 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7708 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7710 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7712 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
7714 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7716 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF
7827 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7828 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7829 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7831 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
7848 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7849 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7850 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7852 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7854 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7856 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7858 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7860 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7862 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7864 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7866 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7868 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7870 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7872 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
7875 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7876 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7877 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7897 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7898 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7899 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7901 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7903 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7905 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7907 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7909 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7911 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7913 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7915 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7917 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7919 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
7922 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7923 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7924 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7943 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7944 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7945 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7947 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7960 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7961 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7962 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7988 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7989 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7990 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7992 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
8001 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
8002 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
8003 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
8005 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
8007 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
8009 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
8011 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
8013 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
8015 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
8018 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
8019 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
8020 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
8022 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
8024 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
8026 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8028 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8030 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
8032 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
8035 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
8036 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
8037 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
8039 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
8041 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
8044 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
8045 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
8046 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
8048 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
8050 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
8053 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
8054 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
8055 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
8057 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
8059 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
8062 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
8063 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
8064 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
8066 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
8068 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
8071 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
8072 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
8073 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
8075 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
8077 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
8080 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
8081 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
8082 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
8084 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
8086 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
8088 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
8091 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
8092 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
8093 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
8095 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
8097 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
8099 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
8101 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
8103 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
8105 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
8108 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
8109 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
8110 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
8112 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
8114 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
8116 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
8118 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
8120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
8122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
8125 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
8129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
8131 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
8133 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
8135 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
8137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
8139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
8142 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
8143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
8146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
8148 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
8150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
8152 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
8154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
8156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
8159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
8160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
8161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
8163 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
8165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
8167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
8169 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
8171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
8173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
8176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
8178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
8180 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
8182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
8184 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
8186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
8188 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
8190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
8193 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
8197 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
8199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
8201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
8203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
8228 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8229 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8230 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8232 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8234 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8236 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8239 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8240 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8241 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8243 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8245 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8247 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8249 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8251 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8253 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8265 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8266 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8267 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8269 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8271 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8273 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8276 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8277 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8278 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8280 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8282 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8284 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8286 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8288 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8290 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8302 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8303 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8304 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8306 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8308 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8310 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8313 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8314 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8315 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8317 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8319 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8321 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8323 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8325 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8327 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8339 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8340 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8341 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
8343 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
8345 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
8347 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8349 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8351 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
8354 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8355 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8356 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
8358 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
8360 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8363 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
8364 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
8365 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
8367 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
8369 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
8372 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
8373 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
8374 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
8376 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
8378 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8380 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
8382 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8385 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8386 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8387 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
8389 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
8391 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
8393 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
8395 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
8397 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
8399 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8402 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8403 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8404 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
8406 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8408 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8410 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8412 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
8414 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8416 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8443 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8444 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8445 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
8447 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
8449 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
8451 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8453 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
8455 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8458 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8459 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8460 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
8462 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8464 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8467 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8468 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
8469 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8471 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
8473 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8476 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8477 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
8478 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8480 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8482 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8484 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
8486 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8489 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8490 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8491 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8493 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8495 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
8497 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8499 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8501 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8503 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8506 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8507 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8508 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8510 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8512 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8514 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8516 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
8518 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8520 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8547 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8548 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8549 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8551 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8553 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8555 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8558 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8559 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
8560 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8562 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8564 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8567 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8568 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8569 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8571 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8573 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8575 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
8577 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
8579 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
8581 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8584 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8585 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8586 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8588 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8590 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8592 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8594 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8596 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8598 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8616 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8617 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8618 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8620 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8622 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8624 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8627 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8628 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8629 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8631 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8633 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8636 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8637 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8638 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8640 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8642 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8644 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8646 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8648 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8650 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8653 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8654 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8655 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8657 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8659 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8661 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8663 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8665 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8667 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8685 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8686 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8687 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8689 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8691 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8693 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8695 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8697 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8699 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8702 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8703 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8704 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8706 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8708 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8710 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8712 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8714 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8716 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8719 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8720 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8721 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8723 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8725 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8728 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8729 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8730 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8732 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8734 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8737 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8738 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
8739 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8741 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8743 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8746 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8747 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8748 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8750 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8752 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8755 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8756 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8757 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8759 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8761 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8764 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8765 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8766 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8768 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8770 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8772 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8775 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8776 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8777 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8779 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8781 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8783 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8785 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8787 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8789 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8792 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8796 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8798 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8800 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8802 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8809 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8815 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8817 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8819 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8826 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8832 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8836 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8847 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8849 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8853 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8864 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8866 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8872 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8881 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8883 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8885 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8887 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8914 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8915 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8916 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8918 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8920 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8922 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8924 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8926 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8928 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8931 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8932 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8933 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8935 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8937 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8939 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8941 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8943 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8945 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8948 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8949 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8950 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8952 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8954 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8957 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8958 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8959 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8961 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8963 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8966 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8967 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8968 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8970 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8972 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8975 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8976 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8977 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8979 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8981 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8984 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8985 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8986 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8988 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8990 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8993 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8994 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8995 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8997 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8999 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9001 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9004 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9005 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
9006 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
9008 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
9010 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
9012 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
9014 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9016 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
9018 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
9021 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
9025 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
9027 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
9029 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
9031 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
9038 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
9044 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
9046 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9048 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9055 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9061 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
9065 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
9076 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9078 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
9082 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
9093 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9095 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9101 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
9110 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
9112 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
9114 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
9116 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
9118 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
9145 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
9146 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
9147 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
9149 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
9151 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
9153 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
9156 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
9157 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
9158 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
9160 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
9162 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
9164 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
9166 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
9168 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
9170 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
9189 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
9190 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
9191 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
9193 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
9195 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
9197 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
9200 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
9201 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
9202 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
9204 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
9206 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
9208 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
9210 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
9212 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
9214 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
9233 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
9234 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
9235 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
9237 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
9239 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
9241 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
9244 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9245 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
9246 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9248 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9250 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9252 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9254 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9256 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9258 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9300 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9301 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9302 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
9304 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
9306 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9308 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9310 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
9312 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
9314 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
9317 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
9318 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
9319 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
9321 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
9323 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
9325 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
9327 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
9329 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
9331 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
9334 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9335 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
9336 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9338 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9340 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9343 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9344 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
9345 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9347 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9349 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9352 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9353 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
9354 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
9356 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
9358 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
9361 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
9362 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
9363 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
9365 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
9367 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
9370 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
9371 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9372 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
9374 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
9376 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
9379 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9380 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9381 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
9383 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9385 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9387 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9390 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9391 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
9392 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9394 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9396 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9398 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9400 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9402 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9404 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
9407 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
9411 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
9413 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
9415 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
9417 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
9424 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
9432 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9434 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
9441 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9451 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9453 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9455 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
9458 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
9459 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
9460 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
9462 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9464 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9466 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
9468 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
9470 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
9472 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
9475 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9477 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
9479 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
9481 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
9483 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9485 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
9487 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9489 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9492 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
9496 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
9498 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
9500 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
9502 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
9504 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
9557 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9558 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9559 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9561 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
9563 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
9565 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9567 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
9569 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9572 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9573 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
9574 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9576 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9578 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9581 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9582 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
9583 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9585 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9587 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9590 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9591 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9592 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9594 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9596 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
9598 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9600 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9603 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9604 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9605 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9607 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9609 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9611 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9613 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9615 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9617 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9620 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9621 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9622 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9624 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9626 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9628 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9630 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9632 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9634 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9693 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9694 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9695 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9697 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9699 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9701 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9703 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9705 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9707 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9821 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9822 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9823 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9825 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9827 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9829 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9831 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9833 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
9871 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9872 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9873 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9900 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9901 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9902 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9948 MPA_RTR_TYPE_NONE = 0,
9964 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9965 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9966 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9968 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9977 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9978 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9979 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9981 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9983 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9985 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9988 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9989 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9990 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9992 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9994 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9996 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9998 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10000 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
10002 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10014 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10015 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10016 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10018 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10020 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10022 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10025 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
10026 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
10027 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
10029 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
10031 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
10034 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10035 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10036 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10038 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10040 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
10042 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
10044 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
10046 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
10048 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
10051 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
10052 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
10053 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10055 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10057 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10059 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
10061 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
10063 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
10065 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
10083 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
10084 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
10085 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10087 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10089 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10091 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10094 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10095 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10096 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10098 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10100 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
10102 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
10104 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10106 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10108 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10139 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10140 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
10141 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10143 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
10149 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10150 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
10151 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10153 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
10161 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
10162 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
10163 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
10165 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
10215 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
10216 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
10217 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
10219 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10221 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10223 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
10225 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
10244 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
10245 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
10246 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10248 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
10250 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
10252 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
10279 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
10280 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
10281 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10283 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10285 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
10287 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
10289 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
10303 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10304 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10305 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
10307 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
10309 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10311 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
10313 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
10315 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
10317 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
10320 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
10321 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
10322 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
10324 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
10326 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
10328 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
10330 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
10332 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
10334 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
10337 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10338 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
10339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10341 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10343 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10346 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
10348 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10350 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10352 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10355 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
10357 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10359 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10361 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
10364 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
10365 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
10366 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
10368 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
10370 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
10373 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
10374 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
10375 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
10377 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
10379 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
10382 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10383 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10384 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
10386 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10388 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10390 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10393 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10394 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
10395 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10397 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10399 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10401 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10403 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10405 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10407 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10410 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10411 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
10414 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
10416 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
10418 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
10427 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
10435 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
10444 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
10445 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
10448 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
10450 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10452 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10454 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10456 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10458 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
10461 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
10462 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
10465 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10467 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10469 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
10471 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
10473 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
10475 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
10478 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
10479 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
10480 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
10482 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10484 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10486 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10488 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10490 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10492 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10495 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
10497 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
10499 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
10501 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
10503 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
10505 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
10507 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10550 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10551 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10552 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10554 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
10556 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
10558 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
10560 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
10562 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10565 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10566 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
10567 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10569 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10571 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10574 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10575 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
10576 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10578 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10580 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10583 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10584 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
10585 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10587 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
10589 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
10591 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10593 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
10596 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10597 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
10598 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10600 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10602 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10604 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10606 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10608 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10610 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10613 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10614 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10615 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10617 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10619 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10621 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10623 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10625 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10627 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10637 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10638 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10639 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10641 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10643 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10645 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10648 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10649 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10650 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10652 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10654 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10657 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10658 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10659 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10661 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10663 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10665 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10667 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10669 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10671 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10674 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10675 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10676 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10678 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10680 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10682 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10684 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10686 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10688 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10708 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10709 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10710 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10712 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10720 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10721 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10722 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10734 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10735 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10736 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10738 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10740 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10742 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10745 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10746 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10747 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10749 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10751 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10753 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10755 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10757 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10759 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10773 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10774 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10775 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10777 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10875 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10876 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10877 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10879 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10881 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10883 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10886 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10887 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10888 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10890 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10892 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10894 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10896 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10898 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10900 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10936 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10937 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10938 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10940 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10942 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10944 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10946 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10948 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10950 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10953 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10954 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10955 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10957 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10959 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10961 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10963 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10965 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10967 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10970 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10971 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10972 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10974 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10976 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10979 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10980 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10981 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10983 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10985 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10988 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10989 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10990 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10992 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10994 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10997 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10998 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10999 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
11001 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
11003 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
11006 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
11007 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
11008 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
11010 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
11012 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
11015 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
11016 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
11017 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
11019 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
11021 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11023 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11026 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11027 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
11028 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11030 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11032 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11034 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11036 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11038 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11040 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
11043 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
11044 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
11047 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
11049 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
11051 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
11060 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
11068 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
11077 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
11078 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11081 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
11083 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11085 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11087 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11089 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
11091 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
11094 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
11095 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
11098 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
11100 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
11102 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
11104 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
11106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
11108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
11111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
11112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
11113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
11115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
11117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
11119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
11121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
11123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
11125 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
11128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
11130 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
11132 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
11134 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
11136 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
11138 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
11140 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
11193 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
11194 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
11195 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11197 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
11199 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
11201 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
11203 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
11205 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11208 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
11209 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
11210 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
11212 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
11214 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11217 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11218 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
11219 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11221 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
11223 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
11226 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
11227 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
11228 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
11230 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11232 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
11234 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
11236 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11239 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11240 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
11241 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11243 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11245 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11247 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11249 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
11251 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
11253 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11256 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11257 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11258 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11260 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11262 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11264 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11266 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11268 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11270 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11290 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11291 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11292 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11294 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11296 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11298 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11301 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
11302 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
11303 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11305 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11307 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11310 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11311 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11312 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11314 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11316 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
11318 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11320 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11322 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11324 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11327 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11328 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11329 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11331 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11333 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11335 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11337 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11339 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11341 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11364 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11365 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11366 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11368 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11370 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11372 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11375 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11376 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11377 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11379 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11381 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11383 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11385 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11387 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11389 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11439 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11440 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11441 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11443 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11445 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11447 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11450 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11451 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11452 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11454 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11456 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11458 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11460 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11462 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11464 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11479 #define MFW_TRACE_SIGNATURE 0x25071946
11482 #define MFW_TRACE_EVENTID_MASK 0x00ffff
11483 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11492 * 0 - just errors will be written to the buffer
11494 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
11516 #define OFFSIZE_OFFSET_SHIFT 0
11517 #define OFFSIZE_OFFSET_MASK 0x0000ffff
11520 #define OFFSIZE_SIZE_MASK 0xffff0000
11540 #define ETH_SPEED_AUTONEG 0x0
11541 #define ETH_SPEED_SMARTLINQ 0x8
11544 #define ETH_PAUSE_NONE 0x0
11545 #define ETH_PAUSE_AUTONEG 0x1
11546 #define ETH_PAUSE_RX 0x2
11547 #define ETH_PAUSE_TX 0x4
11552 #define ETH_LOOPBACK_NONE 0x0
11553 #define ETH_LOOPBACK_INT_PHY 0x1
11554 #define ETH_LOOPBACK_EXT_PHY 0x2
11555 #define ETH_LOOPBACK_EXT 0x3
11556 #define ETH_LOOPBACK_MAC 0x4
11557 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 0x5
11558 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 0x6
11559 #define ETH_LOOPBACK_PCS_AH_ONLY 0x7
11560 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY 0x8
11561 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY 0x9
11564 #define EEE_CFG_EEE_ENABLED BIT(0)
11568 #define EEE_TX_TIMER_USEC_MASK 0xfffffff0
11570 #define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00
11571 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100
11572 #define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000
11577 #define FEC_FORCE_MODE_MASK 0x000000ff
11578 #define FEC_FORCE_MODE_OFFSET 0
11579 #define FEC_FORCE_MODE_NONE 0x00
11580 #define FEC_FORCE_MODE_FIRECODE 0x01
11581 #define FEC_FORCE_MODE_RS 0x02
11582 #define FEC_FORCE_MODE_AUTO 0x07
11583 #define FEC_EXTENDED_MODE_MASK 0xffffff00
11585 #define ETH_EXT_FEC_NONE 0x00000100
11586 #define ETH_EXT_FEC_10G_NONE 0x00000200
11587 #define ETH_EXT_FEC_10G_BASE_R 0x00000400
11588 #define ETH_EXT_FEC_20G_NONE 0x00000800
11589 #define ETH_EXT_FEC_20G_BASE_R 0x00001000
11590 #define ETH_EXT_FEC_25G_NONE 0x00002000
11591 #define ETH_EXT_FEC_25G_BASE_R 0x00004000
11592 #define ETH_EXT_FEC_25G_RS528 0x00008000
11593 #define ETH_EXT_FEC_40G_NONE 0x00010000
11594 #define ETH_EXT_FEC_40G_BASE_R 0x00020000
11595 #define ETH_EXT_FEC_50G_NONE 0x00040000
11596 #define ETH_EXT_FEC_50G_BASE_R 0x00080000
11597 #define ETH_EXT_FEC_50G_RS528 0x00100000
11598 #define ETH_EXT_FEC_50G_RS544 0x00200000
11599 #define ETH_EXT_FEC_100G_NONE 0x00400000
11600 #define ETH_EXT_FEC_100G_BASE_R 0x00800000
11601 #define ETH_EXT_FEC_100G_RS528 0x01000000
11602 #define ETH_EXT_FEC_100G_RS544 0x02000000
11605 #define ETH_EXT_SPEED_MASK 0x0000ffff
11606 #define ETH_EXT_SPEED_OFFSET 0
11607 #define ETH_EXT_SPEED_AN 0x00000001
11608 #define ETH_EXT_SPEED_1G 0x00000002
11609 #define ETH_EXT_SPEED_10G 0x00000004
11610 #define ETH_EXT_SPEED_20G 0x00000008
11611 #define ETH_EXT_SPEED_25G 0x00000010
11612 #define ETH_EXT_SPEED_40G 0x00000020
11613 #define ETH_EXT_SPEED_50G_BASE_R 0x00000040
11614 #define ETH_EXT_SPEED_50G_BASE_R2 0x00000080
11615 #define ETH_EXT_SPEED_100G_BASE_R2 0x00000100
11616 #define ETH_EXT_SPEED_100G_BASE_R4 0x00000200
11617 #define ETH_EXT_SPEED_100G_BASE_P4 0x00000400
11618 #define ETH_EXT_ADV_SPEED_MASK 0xffff0000
11620 #define ETH_EXT_ADV_SPEED_RESERVED 0x00010000
11621 #define ETH_EXT_ADV_SPEED_1G 0x00020000
11622 #define ETH_EXT_ADV_SPEED_10G 0x00040000
11623 #define ETH_EXT_ADV_SPEED_20G 0x00080000
11624 #define ETH_EXT_ADV_SPEED_25G 0x00100000
11625 #define ETH_EXT_ADV_SPEED_40G 0x00200000
11626 #define ETH_EXT_ADV_SPEED_50G_BASE_R 0x00400000
11627 #define ETH_EXT_ADV_SPEED_50G_BASE_R2 0x00800000
11628 #define ETH_EXT_ADV_SPEED_100G_BASE_R2 0x01000000
11629 #define ETH_EXT_ADV_SPEED_100G_BASE_R4 0x02000000
11630 #define ETH_EXT_ADV_SPEED_100G_BASE_P4 0x04000000
11635 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
11636 #define PORT_MF_CFG_OV_TAG_SHIFT 0
11737 #define PORT_CMT_IN_TEAM (1 << 0)
11740 #define PORT_CMT_PORT_INACTIVE (0 << 1)
11744 #define PORT_CMT_TEAM0 (0 << 2)
11754 LLDP_NEAREST_BRIDGE = 0,
11762 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
11763 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
11764 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
11766 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
11768 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
11770 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
11786 #define DCBX_ETS_ENABLED_MASK 0x00000001
11787 #define DCBX_ETS_ENABLED_SHIFT 0
11788 #define DCBX_ETS_WILLING_MASK 0x00000002
11790 #define DCBX_ETS_ERROR_MASK 0x00000004
11792 #define DCBX_ETS_CBS_MASK 0x00000008
11794 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
11796 #define DCBX_OOO_TC_MASK 0x00000f00
11802 #define DCBX_CEE_STRICT_PRIORITY 0xf
11805 #define DCBX_ETS_TSA_STRICT 0
11815 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
11816 #define DCBX_APP_PRI_MAP_SHIFT 0
11817 #define DCBX_APP_PRI_0 0x01
11818 #define DCBX_APP_PRI_1 0x02
11819 #define DCBX_APP_PRI_2 0x04
11820 #define DCBX_APP_PRI_3 0x08
11821 #define DCBX_APP_PRI_4 0x10
11822 #define DCBX_APP_PRI_5 0x20
11823 #define DCBX_APP_PRI_6 0x40
11824 #define DCBX_APP_PRI_7 0x80
11825 #define DCBX_APP_SF_MASK 0x00000300
11827 #define DCBX_APP_SF_ETHTYPE 0
11829 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
11831 #define DCBX_APP_SF_IEEE_RESERVED 0
11837 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
11843 #define DCBX_APP_ENABLED_MASK 0x00000001
11844 #define DCBX_APP_ENABLED_SHIFT 0
11845 #define DCBX_APP_WILLING_MASK 0x00000002
11847 #define DCBX_APP_ERROR_MASK 0x00000004
11849 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
11851 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
11859 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
11860 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
11861 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
11862 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
11863 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
11864 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
11865 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
11866 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
11867 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
11868 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
11870 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
11872 #define DCBX_PFC_CAPS_MASK 0x00000f00
11874 #define DCBX_PFC_MBC_MASK 0x00004000
11876 #define DCBX_PFC_WILLING_MASK 0x00008000
11878 #define DCBX_PFC_ENABLED_MASK 0x00010000
11880 #define DCBX_PFC_ERROR_MASK 0x00020000
11888 #define DCBX_CONFIG_VERSION_MASK 0x00000007
11889 #define DCBX_CONFIG_VERSION_SHIFT 0
11890 #define DCBX_CONFIG_VERSION_DISABLED 0
11914 #define DCB_DSCP_ENABLE_MASK 0x1
11915 #define DCB_DSCP_ENABLE_SHIFT 0
11951 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
11952 #define PROCESS_KILL_COUNTER_SHIFT 0
11953 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
11962 #define LINK_STATUS_LINK_UP 0x00000001
11963 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
11972 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
11973 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
11974 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
11975 #define LINK_STATUS_PFC_ENABLED 0x00000100
11976 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
11977 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
11978 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
11979 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
11980 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
11981 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
11982 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
11983 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
11984 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000
11985 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
11989 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
11990 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
11991 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
11992 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
11993 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
11994 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
11995 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
11997 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
11998 #define LINK_STATUS_FEC_MODE_NONE (0 << 27)
12014 #define MEDIA_UNSPECIFIED 0x0
12015 #define MEDIA_SFPP_10G_FIBER 0x1
12016 #define MEDIA_XFP_FIBER 0x2
12017 #define MEDIA_DA_TWINAX 0x3
12018 #define MEDIA_BASE_T 0x4
12019 #define MEDIA_SFP_1G_FIBER 0x5
12020 #define MEDIA_MODULE_FIBER 0x6
12021 #define MEDIA_KR 0xf0
12022 #define MEDIA_NOT_PRESENT 0xff
12039 #define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
12040 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
12041 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
12042 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
12043 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
12044 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
12045 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
12046 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
12047 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
12048 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
12049 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
12050 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
12051 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
12052 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
12053 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
12054 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
12055 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
12056 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
12057 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
12058 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
12059 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
12060 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
12061 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
12062 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
12063 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
12064 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
12065 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
12066 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
12067 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
12068 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
12069 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
12070 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
12071 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
12072 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
12073 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
12074 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
12075 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
12076 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
12077 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
12078 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
12079 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
12080 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
12081 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
12082 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
12083 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
12084 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
12085 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
12086 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
12087 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
12088 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
12089 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
12090 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
12091 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37
12092 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38
12093 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39
12094 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a
12102 #define EEE_ACTIVE_BIT BIT(0)
12103 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
12107 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
12109 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
12115 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
12116 #define EEE_REMOTE_TW_TX_OFFSET 0
12117 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
12122 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
12123 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
12124 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
12125 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
12126 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
12128 #define OEM_CFG_SCHED_TYPE_ETS 0x1
12129 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
12140 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
12141 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
12142 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
12144 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
12146 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
12147 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
12148 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
12149 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
12150 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
12152 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
12154 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
12155 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
12157 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
12160 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
12163 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
12164 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
12167 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
12176 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
12177 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
12189 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
12190 #define DRV_ID_PDA_COMP_VER_SHIFT 0
12193 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
12198 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
12200 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
12203 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
12208 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
12209 #define OEM_CFG_FUNC_TC_OFFSET 0
12210 #define OEM_CFG_FUNC_TC_0 0x0
12211 #define OEM_CFG_FUNC_TC_1 0x1
12212 #define OEM_CFG_FUNC_TC_2 0x2
12213 #define OEM_CFG_FUNC_TC_3 0x3
12214 #define OEM_CFG_FUNC_TC_4 0x4
12215 #define OEM_CFG_FUNC_TC_5 0x5
12216 #define OEM_CFG_FUNC_TC_6 0x6
12217 #define OEM_CFG_FUNC_TC_7 0x7
12219 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
12221 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
12222 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
12291 RESOURCE_NUM_SB_E = 0,
12315 RESOURCE_NUM_INVALID = 0xFFFFFFFF
12328 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12331 #define DRV_ROLE_NONE 0
12341 #define LOAD_REQ_ROLE_MASK 0x000000FF
12342 #define LOAD_REQ_ROLE_SHIFT 0
12343 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
12345 #define LOAD_REQ_LOCK_TO_DEFAULT 0
12347 #define LOAD_REQ_FORCE_MASK 0x000F0000
12349 #define LOAD_REQ_FORCE_NONE 0
12352 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
12354 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
12362 #define LOAD_RSP_ROLE_MASK 0x000000FF
12363 #define LOAD_RSP_ROLE_SHIFT 0
12364 #define LOAD_RSP_HSI_MASK 0x0000FF00
12366 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
12368 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
12405 #define DRV_MSG_CODE_MASK 0xffff0000
12406 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
12407 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
12408 #define DRV_MSG_CODE_INIT_HW 0x12000000
12409 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
12410 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
12411 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
12412 #define DRV_MSG_CODE_INIT_PHY 0x22000000
12413 #define DRV_MSG_CODE_LINK_RESET 0x23000000
12414 #define DRV_MSG_CODE_SET_DCBX 0x25000000
12415 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
12416 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
12417 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
12418 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
12419 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
12420 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12421 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
12422 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
12423 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
12424 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
12425 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
12426 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
12428 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12429 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
12430 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
12431 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000
12432 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000
12433 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
12434 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
12435 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
12436 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
12437 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
12438 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
12439 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
12440 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
12441 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
12442 #define DRV_MSG_CODE_MCP_RESET 0x00090000
12443 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
12444 #define DRV_MSG_CODE_MCP_HALT 0x00100000
12445 #define DRV_MSG_CODE_SET_VMAC 0x00110000
12446 #define DRV_MSG_CODE_GET_VMAC 0x00120000
12448 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
12453 #define DRV_MSG_CODE_GET_STATS 0x00130000
12459 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
12461 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
12463 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
12464 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
12465 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
12466 /* Send crash dump commands with param[3:0] - opcode */
12467 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000
12468 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000
12469 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000
12470 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
12472 #define DRV_MSG_CODE_DEBUG_DATA_SEND 0xc0040000
12474 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
12475 #define RESOURCE_CMD_REQ_RESC_SHIFT 0
12476 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
12483 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
12486 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
12487 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0
12488 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
12497 #define RESOURCE_DUMP 0
12500 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
12501 #define DRV_MSG_CODE_MDUMP_ACK 0x01
12502 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
12503 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
12504 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
12505 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
12506 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06
12507 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07
12508 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08
12510 #define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a
12511 #define DRV_MSG_CODE_MDUMP_GEN_MDUMP2 0x0b
12512 #define DRV_MSG_CODE_MDUMP_FREE_MDUMP2 0x0c
12514 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
12515 #define DRV_MSG_CODE_OS_WOL 0x002e0000
12517 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
12518 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
12519 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
12522 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
12523 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
12524 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
12525 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
12526 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
12529 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
12530 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
12531 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
12533 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
12535 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
12536 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
12538 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
12539 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
12540 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
12542 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
12543 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
12544 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
12549 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
12550 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
12551 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
12552 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
12553 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
12554 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
12556 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
12557 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
12558 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
12559 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
12560 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
12561 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
12562 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
12564 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
12565 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
12577 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
12578 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
12579 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
12581 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
12582 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
12584 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
12585 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
12586 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
12588 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
12589 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
12591 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc
12593 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00
12595 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000
12598 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12600 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12601 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12608 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
12613 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
12614 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff
12616 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00
12618 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff
12619 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
12620 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
12621 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004
12622 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL 0x00000008
12623 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
12626 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
12627 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff
12630 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
12631 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff
12633 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000
12635 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
12636 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
12637 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff
12639 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
12641 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
12643 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
12645 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
12647 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
12649 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
12652 #define FW_MSG_CODE_MASK 0xffff0000
12653 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
12654 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
12655 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
12656 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
12657 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
12658 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
12659 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
12660 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
12661 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12662 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
12663 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
12664 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
12665 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
12666 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
12667 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
12668 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
12669 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
12670 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
12671 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
12672 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
12674 #define FW_MSG_CODE_NVM_OK 0x00010000
12675 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
12676 #define FW_MSG_CODE_PHY_OK 0x00110000
12677 #define FW_MSG_CODE_OK 0x00160000
12678 #define FW_MSG_CODE_ERROR 0x00170000
12679 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
12680 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
12681 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
12683 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
12684 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
12685 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
12686 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
12688 #define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG 0xb0070000
12689 #define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL 0xb0080000
12690 #define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF 0xb0090000
12691 #define FW_MSG_CODE_DEBUG_NOT_ENABLED 0xb00a0000
12692 #define FW_MSG_CODE_DEBUG_DATA_SEND_OK 0xb00b0000
12694 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
12697 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12699 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12700 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12703 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
12704 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
12705 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
12706 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
12709 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0)
12715 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
12717 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
12718 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
12719 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
12721 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
12723 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
12726 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
12727 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
12730 #define DRV_PULSE_SEQ_MASK 0x00007fff
12731 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
12732 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
12735 #define MCP_PULSE_SEQ_MASK 0x00007fff
12736 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
12737 #define MCP_EVENT_MASK 0xffff0000
12738 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
12743 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
12744 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
12745 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
12773 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
12774 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
13034 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
13035 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
13042 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
13044 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
13045 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
13046 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
13047 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
13048 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
13049 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
13050 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
13051 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
13060 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
13061 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
13062 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
13063 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
13064 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
13065 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
13066 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
13067 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
13068 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
13069 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
13070 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
13071 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
13072 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
13073 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11
13074 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12
13075 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13
13076 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14
13077 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15
13100 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
13101 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
13102 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
13104 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
13111 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
13112 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
13113 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
13114 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
13132 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
13134 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
13135 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
13136 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
13137 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
13138 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
13140 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
13141 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
13142 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
13148 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
13149 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
13150 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
13151 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
13152 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
13153 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
13154 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
13155 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
13156 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
13159 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
13160 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
13161 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
13162 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
13163 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
13164 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
13165 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
13166 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
13167 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
13168 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
13169 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
13170 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
13172 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
13173 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
13174 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
13175 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000
13177 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
13178 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
13179 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
13180 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
13187 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
13189 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
13190 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
13191 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
13192 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
13203 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
13204 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
13205 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
13206 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
13207 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
13208 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
13209 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
13231 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff
13232 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
13233 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1
13234 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
13235 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
13236 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8
13237 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10
13238 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20
13239 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40
13240 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80
13241 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100
13242 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200
13243 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400
13244 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000
13246 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1
13247 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
13248 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
13249 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8
13250 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10
13251 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20
13252 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40
13253 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80
13254 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100
13255 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200
13256 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400
13328 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
13329 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
13330 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
13332 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
13334 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
13341 #define NVM_MAGIC_VALUE 0x669955aa
13344 NVM_TYPE_TIM1 = 0x01,
13345 NVM_TYPE_TIM2 = 0x02,
13346 NVM_TYPE_MIM1 = 0x03,
13347 NVM_TYPE_MIM2 = 0x04,
13348 NVM_TYPE_MBA = 0x05,
13349 NVM_TYPE_MODULES_PN = 0x06,
13350 NVM_TYPE_VPD = 0x07,
13351 NVM_TYPE_MFW_TRACE1 = 0x08,
13352 NVM_TYPE_MFW_TRACE2 = 0x09,
13353 NVM_TYPE_NVM_CFG1 = 0x0a,
13354 NVM_TYPE_L2B = 0x0b,
13355 NVM_TYPE_DIR1 = 0x0c,
13356 NVM_TYPE_EAGLE_FW1 = 0x0d,
13357 NVM_TYPE_FALCON_FW1 = 0x0e,
13358 NVM_TYPE_PCIE_FW1 = 0x0f,
13359 NVM_TYPE_HW_SET = 0x10,
13360 NVM_TYPE_LIM = 0x11,
13361 NVM_TYPE_AVS_FW1 = 0x12,
13362 NVM_TYPE_DIR2 = 0x13,
13363 NVM_TYPE_CCM = 0x14,
13364 NVM_TYPE_EAGLE_FW2 = 0x15,
13365 NVM_TYPE_FALCON_FW2 = 0x16,
13366 NVM_TYPE_PCIE_FW2 = 0x17,
13367 NVM_TYPE_AVS_FW2 = 0x18,
13368 NVM_TYPE_INIT_HW = 0x19,
13369 NVM_TYPE_DEFAULT_CFG = 0x1a,
13370 NVM_TYPE_MDUMP = 0x1b,
13371 NVM_TYPE_META = 0x1c,
13372 NVM_TYPE_ISCSI_CFG = 0x1d,
13373 NVM_TYPE_FCOE_CFG = 0x1f,
13374 NVM_TYPE_ETH_PHY_FW1 = 0x20,
13375 NVM_TYPE_ETH_PHY_FW2 = 0x21,
13376 NVM_TYPE_BDN = 0x22,
13377 NVM_TYPE_8485X_PHY_FW = 0x23,
13378 NVM_TYPE_PUB_KEY = 0x24,
13379 NVM_TYPE_RECOVERY = 0x25,
13380 NVM_TYPE_PLDM = 0x26,
13381 NVM_TYPE_UPK1 = 0x27,
13382 NVM_TYPE_UPK2 = 0x28,
13383 NVM_TYPE_MASTER_KC = 0x29,
13384 NVM_TYPE_BACKUP_KC = 0x2a,
13385 NVM_TYPE_HW_DUMP = 0x2b,
13386 NVM_TYPE_HW_DUMP_OUT = 0x2c,
13387 NVM_TYPE_BIN_NVM_META = 0x30,
13388 NVM_TYPE_ROM_TEST = 0xf0,
13389 NVM_TYPE_88X33X0_PHY_FW = 0x31,
13390 NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13394 #define DIR_ID_1 (0)