1138 #define MII_READ	(-1)  macro
1158 	if (value != MII_READ) {  in mii_rw()
1167 	} else if (value != MII_READ) {  in mii_rw()
1195 		miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_reset()
1242 	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);  in init_realtek_8211c()
1249 	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);  in init_realtek_8211c()
1268 				      PHY_REALTEK_INIT_REG6, MII_READ);  in init_realtek_8201()
1287 				      PHY_REALTEK_INIT_REG2, MII_READ);  in init_realtek_8201_cross()
1307 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1312 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1317 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1336 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1340 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1352 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1358 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1368 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1372 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1396 		reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in phy_init()
1429 	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in phy_init()
1443 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in phy_init()
1447 					  MII_CTRL1000, MII_READ);  in phy_init()
1462 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_init()
1522 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_init()
3319 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_force_linkspeed()
3403 	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_update_linkspeed()
3416 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_update_linkspeed()
3417 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_update_linkspeed()
3452 	adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_update_linkspeed()
3453 	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);  in nv_update_linkspeed()
3457 		control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_update_linkspeed()
3458 		status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);  in nv_update_linkspeed()
3525 	phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */  in nv_update_linkspeed()
4383 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_get_link_ksettings()
4393 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_get_link_ksettings()
4488 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_link_ksettings()
4505 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_set_link_ksettings()
4514 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_link_ksettings()
4532 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_link_ksettings()
4555 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_set_link_ksettings()
4560 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_link_ksettings()
4634 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_nway_reset()
4840 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_pauseparam()
4850 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_pauseparam()
4881 	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_loopback()
5035 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_link_test()
5036 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_link_test()
5466 	       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);  in nv_open()
5665 		       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);  in nv_close()
6053 		id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);  in nv_probe()
6058 		id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);  in nv_probe()
6074 			np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;  in nv_probe()
6088 		u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_probe()
6168 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6175 		mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_restore_phy()