Lines Matching +full:0 +full:x0000001
66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet form…
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
76 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
77 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
78 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
79 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 …
80 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
81 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
82 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
83 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
84 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
85 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
86 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
87 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
88 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
89 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
90 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
91 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
92 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
95 NvRegIrqStatus = 0x000,
96 #define NVREG_IRQSTAT_MIIEVENT 0x040
97 #define NVREG_IRQSTAT_MASK 0x83ff
98 NvRegIrqMask = 0x004,
99 #define NVREG_IRQ_RX_ERROR 0x0001
100 #define NVREG_IRQ_RX 0x0002
101 #define NVREG_IRQ_RX_NOBUF 0x0004
102 #define NVREG_IRQ_TX_ERR 0x0008
103 #define NVREG_IRQ_TX_OK 0x0010
104 #define NVREG_IRQ_TIMER 0x0020
105 #define NVREG_IRQ_LINK 0x0040
106 #define NVREG_IRQ_RX_FORCED 0x0080
107 #define NVREG_IRQ_TX_FORCED 0x0100
108 #define NVREG_IRQ_RECOVER_ERROR 0x8200
109 #define NVREG_IRQMASK_THROUGHPUT 0x00df
110 #define NVREG_IRQMASK_CPU 0x0060
115 NvRegUnknownSetupReg6 = 0x008,
122 NvRegPollingInterval = 0x00c,
125 NvRegMSIMap0 = 0x020,
126 NvRegMSIMap1 = 0x024,
127 NvRegMSIIrqMask = 0x030,
128 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
129 NvRegMisc1 = 0x080,
130 #define NVREG_MISC1_PAUSE_TX 0x01
131 #define NVREG_MISC1_HD 0x02
132 #define NVREG_MISC1_FORCE 0x3b0f3c
134 NvRegMacReset = 0x34,
135 #define NVREG_MAC_RESET_ASSERT 0x0F3
136 NvRegTransmitterControl = 0x084,
137 #define NVREG_XMITCTL_START 0x01
138 #define NVREG_XMITCTL_MGMT_ST 0x40000000
139 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
140 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
141 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
142 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
143 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
144 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
145 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
146 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
147 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
148 #define NVREG_XMITCTL_DATA_START 0x00100000
149 #define NVREG_XMITCTL_DATA_READY 0x00010000
150 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
151 NvRegTransmitterStatus = 0x088,
152 #define NVREG_XMITSTAT_BUSY 0x01
154 NvRegPacketFilterFlags = 0x8c,
155 #define NVREG_PFF_PAUSE_RX 0x08
156 #define NVREG_PFF_ALWAYS 0x7F0000
157 #define NVREG_PFF_PROMISC 0x80
158 #define NVREG_PFF_MYADDR 0x20
159 #define NVREG_PFF_LOOPBACK 0x10
161 NvRegOffloadConfig = 0x90,
162 #define NVREG_OFFLOAD_HOMEPHY 0x601
164 NvRegReceiverControl = 0x094,
165 #define NVREG_RCVCTL_START 0x01
166 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
167 NvRegReceiverStatus = 0x98,
168 #define NVREG_RCVSTAT_BUSY 0x01
170 NvRegSlotTime = 0x9c,
171 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
172 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
173 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
174 #define NVREG_SLOTTIME_HALF 0x0000ff00
175 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
176 #define NVREG_SLOTTIME_MASK 0x000000ff
178 NvRegTxDeferral = 0xA0,
179 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
180 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
181 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
182 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
183 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
184 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
185 NvRegRxDeferral = 0xA4,
186 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
187 NvRegMacAddrA = 0xA8,
188 NvRegMacAddrB = 0xAC,
189 NvRegMulticastAddrA = 0xB0,
190 #define NVREG_MCASTADDRA_FORCE 0x01
191 NvRegMulticastAddrB = 0xB4,
192 NvRegMulticastMaskA = 0xB8,
193 #define NVREG_MCASTMASKA_NONE 0xffffffff
194 NvRegMulticastMaskB = 0xBC,
195 #define NVREG_MCASTMASKB_NONE 0xffff
197 NvRegPhyInterface = 0xC0,
198 #define PHY_RGMII 0x10000000
199 NvRegBackOffControl = 0xC4,
200 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
201 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
205 NvRegTxRingPhysAddr = 0x100,
206 NvRegRxRingPhysAddr = 0x104,
207 NvRegRingSizes = 0x108,
208 #define NVREG_RINGSZ_TXSHIFT 0
210 NvRegTransmitPoll = 0x10c,
211 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
212 NvRegLinkSpeed = 0x110,
213 #define NVREG_LINKSPEED_FORCE 0x10000
217 #define NVREG_LINKSPEED_MASK (0xFFF)
218 NvRegUnknownSetupReg5 = 0x130,
220 NvRegTxWatermark = 0x13c,
221 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
222 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
223 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
224 NvRegTxRxControl = 0x144,
225 #define NVREG_TXRXCTL_KICK 0x0001
226 #define NVREG_TXRXCTL_BIT1 0x0002
227 #define NVREG_TXRXCTL_BIT2 0x0004
228 #define NVREG_TXRXCTL_IDLE 0x0008
229 #define NVREG_TXRXCTL_RESET 0x0010
230 #define NVREG_TXRXCTL_RXCHECK 0x0400
231 #define NVREG_TXRXCTL_DESC_1 0
232 #define NVREG_TXRXCTL_DESC_2 0x002100
233 #define NVREG_TXRXCTL_DESC_3 0xc02200
234 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
235 #define NVREG_TXRXCTL_VLANINS 0x00080
236 NvRegTxRingPhysAddrHigh = 0x148,
237 NvRegRxRingPhysAddrHigh = 0x14C,
238 NvRegTxPauseFrame = 0x170,
239 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
240 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
241 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
242 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
243 NvRegTxPauseFrameLimit = 0x174,
244 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
245 NvRegMIIStatus = 0x180,
246 #define NVREG_MIISTAT_ERROR 0x0001
247 #define NVREG_MIISTAT_LINKCHANGE 0x0008
248 #define NVREG_MIISTAT_MASK_RW 0x0007
249 #define NVREG_MIISTAT_MASK_ALL 0x000f
250 NvRegMIIMask = 0x184,
251 #define NVREG_MII_LINKCHANGE 0x0008
253 NvRegAdapterControl = 0x188,
254 #define NVREG_ADAPTCTL_START 0x02
255 #define NVREG_ADAPTCTL_LINKUP 0x04
256 #define NVREG_ADAPTCTL_PHYVALID 0x40000
257 #define NVREG_ADAPTCTL_RUNNING 0x100000
259 NvRegMIISpeed = 0x18c,
262 NvRegMIIControl = 0x190,
263 #define NVREG_MIICTL_INUSE 0x08000
264 #define NVREG_MIICTL_WRITE 0x00400
266 NvRegMIIData = 0x194,
267 NvRegTxUnicast = 0x1a0,
268 NvRegTxMulticast = 0x1a4,
269 NvRegTxBroadcast = 0x1a8,
270 NvRegWakeUpFlags = 0x200,
271 #define NVREG_WAKEUPFLAGS_VAL 0x7770
277 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
278 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
279 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
280 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
281 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
283 NvRegMgmtUnitGetVersion = 0x204,
284 #define NVREG_MGMTUNITGETVERSION 0x01
285 NvRegMgmtUnitVersion = 0x208,
286 #define NVREG_MGMTUNITVERSION 0x08
287 NvRegPowerCap = 0x268,
291 NvRegPowerState = 0x26c,
292 #define NVREG_POWERSTATE_POWEREDUP 0x8000
293 #define NVREG_POWERSTATE_VALID 0x0100
294 #define NVREG_POWERSTATE_MASK 0x0003
295 #define NVREG_POWERSTATE_D0 0x0000
296 #define NVREG_POWERSTATE_D1 0x0001
297 #define NVREG_POWERSTATE_D2 0x0002
298 #define NVREG_POWERSTATE_D3 0x0003
299 NvRegMgmtUnitControl = 0x278,
300 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
301 NvRegTxCnt = 0x280,
302 NvRegTxZeroReXmt = 0x284,
303 NvRegTxOneReXmt = 0x288,
304 NvRegTxManyReXmt = 0x28c,
305 NvRegTxLateCol = 0x290,
306 NvRegTxUnderflow = 0x294,
307 NvRegTxLossCarrier = 0x298,
308 NvRegTxExcessDef = 0x29c,
309 NvRegTxRetryErr = 0x2a0,
310 NvRegRxFrameErr = 0x2a4,
311 NvRegRxExtraByte = 0x2a8,
312 NvRegRxLateCol = 0x2ac,
313 NvRegRxRunt = 0x2b0,
314 NvRegRxFrameTooLong = 0x2b4,
315 NvRegRxOverflow = 0x2b8,
316 NvRegRxFCSErr = 0x2bc,
317 NvRegRxFrameAlignErr = 0x2c0,
318 NvRegRxLenErr = 0x2c4,
319 NvRegRxUnicast = 0x2c8,
320 NvRegRxMulticast = 0x2cc,
321 NvRegRxBroadcast = 0x2d0,
322 NvRegTxDef = 0x2d4,
323 NvRegTxFrame = 0x2d8,
324 NvRegRxCnt = 0x2dc,
325 NvRegTxPause = 0x2e0,
326 NvRegRxPause = 0x2e4,
327 NvRegRxDropFrame = 0x2e8,
328 NvRegVlanControl = 0x300,
329 #define NVREG_VLANCONTROL_ENABLE 0x2000
330 NvRegMSIXMap0 = 0x3e0,
331 NvRegMSIXMap1 = 0x3e4,
332 NvRegMSIXIrqStatus = 0x3f0,
334 NvRegPowerState2 = 0x600,
335 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
336 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
337 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
338 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
359 #define FLAG_MASK_V1 0xffff0000
360 #define FLAG_MASK_V2 0xffffc000
361 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
362 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
366 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
377 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
409 #define NV_RX2_CHECKSUMMASK (0x1C000000)
410 #define NV_RX2_CHECKSUM_IP (0x10000000)
411 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
412 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
428 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
431 #define NV_PCI_REGSZ_VER1 0x270
432 #define NV_PCI_REGSZ_VER2 0x2d4
433 #define NV_PCI_REGSZ_VER3 0x604
434 #define NV_PCI_REGSZ_MAX 0x604
492 #define PHY_OUI_MARVELL 0x5043
493 #define PHY_OUI_CICADA 0x03f1
494 #define PHY_OUI_VITESSE 0x01c1
495 #define PHY_OUI_REALTEK 0x0732
496 #define PHY_OUI_REALTEK2 0x0020
497 #define PHYID1_OUI_MASK 0x03ff
499 #define PHYID2_OUI_MASK 0xfc00
501 #define PHYID2_MODEL_MASK 0x03f0
502 #define PHY_MODEL_REALTEK_8211 0x0110
503 #define PHY_REV_MASK 0x0001
504 #define PHY_REV_REALTEK_8211B 0x0000
505 #define PHY_REV_REALTEK_8211C 0x0001
506 #define PHY_MODEL_REALTEK_8201 0x0200
507 #define PHY_MODEL_MARVELL_E3016 0x0220
508 #define PHY_MARVELL_E3016_INITMASK 0x0300
509 #define PHY_CICADA_INIT1 0x0f000
510 #define PHY_CICADA_INIT2 0x0e00
511 #define PHY_CICADA_INIT3 0x01000
512 #define PHY_CICADA_INIT4 0x0200
513 #define PHY_CICADA_INIT5 0x0004
514 #define PHY_CICADA_INIT6 0x02000
515 #define PHY_VITESSE_INIT_REG1 0x1f
516 #define PHY_VITESSE_INIT_REG2 0x10
517 #define PHY_VITESSE_INIT_REG3 0x11
518 #define PHY_VITESSE_INIT_REG4 0x12
519 #define PHY_VITESSE_INIT_MSK1 0xc
520 #define PHY_VITESSE_INIT_MSK2 0x0180
521 #define PHY_VITESSE_INIT1 0x52b5
522 #define PHY_VITESSE_INIT2 0xaf8a
523 #define PHY_VITESSE_INIT3 0x8
524 #define PHY_VITESSE_INIT4 0x8f8a
525 #define PHY_VITESSE_INIT5 0xaf86
526 #define PHY_VITESSE_INIT6 0x8f86
527 #define PHY_VITESSE_INIT7 0xaf82
528 #define PHY_VITESSE_INIT8 0x0100
529 #define PHY_VITESSE_INIT9 0x8f82
530 #define PHY_VITESSE_INIT10 0x0
531 #define PHY_REALTEK_INIT_REG1 0x1f
532 #define PHY_REALTEK_INIT_REG2 0x19
533 #define PHY_REALTEK_INIT_REG3 0x13
534 #define PHY_REALTEK_INIT_REG4 0x14
535 #define PHY_REALTEK_INIT_REG5 0x18
536 #define PHY_REALTEK_INIT_REG6 0x11
537 #define PHY_REALTEK_INIT_REG7 0x01
538 #define PHY_REALTEK_INIT1 0x0000
539 #define PHY_REALTEK_INIT2 0x8e00
540 #define PHY_REALTEK_INIT3 0x0001
541 #define PHY_REALTEK_INIT4 0xad17
542 #define PHY_REALTEK_INIT5 0xfb54
543 #define PHY_REALTEK_INIT6 0xf5c7
544 #define PHY_REALTEK_INIT7 0x1000
545 #define PHY_REALTEK_INIT8 0x0003
546 #define PHY_REALTEK_INIT9 0x0008
547 #define PHY_REALTEK_INIT10 0x0005
548 #define PHY_REALTEK_INIT11 0x0200
549 #define PHY_REALTEK_INIT_MSK1 0x0003
551 #define PHY_GIGABIT 0x0100
553 #define PHY_TIMEOUT 0x1
554 #define PHY_ERROR 0x2
556 #define PHY_100 0x1
557 #define PHY_1000 0x2
558 #define PHY_HALF 0x100
560 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
561 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
562 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
563 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
564 #define NV_PAUSEFRAME_RX_REQ 0x0010
565 #define NV_PAUSEFRAME_TX_REQ 0x0020
566 #define NV_PAUSEFRAME_AUTONEG 0x0040
570 #define NV_MSI_X_VECTORS_MASK 0x000f
571 #define NV_MSI_CAPABLE 0x0010
572 #define NV_MSI_X_CAPABLE 0x0020
573 #define NV_MSI_ENABLED 0x0040
574 #define NV_MSI_X_ENABLED 0x0080
576 #define NV_MSI_X_VECTOR_ALL 0x0
577 #define NV_MSI_X_VECTOR_RX 0x0
578 #define NV_MSI_X_VECTOR_TX 0x1
579 #define NV_MSI_X_VECTOR_OTHER 0x2
581 #define NV_MSI_PRIV_OFFSET 0x68
582 #define NV_MSI_PRIV_VALUE 0xffffffff
584 #define NV_RESTART_TX 0x1
585 #define NV_RESTART_RX 0x2
698 { NvRegUnknownSetupReg6, 0x01 },
699 { NvRegMisc1, 0x03c },
700 { NvRegOffloadConfig, 0x03ff },
701 { NvRegMulticastAddrA, 0xffffffff },
702 { NvRegTxWatermark, 0x0ff },
703 { NvRegWakeUpFlags, 0x07777 },
704 { 0, 0 }
882 * Min = 0, and Max = 65535
977 if (delaymax < 0) in reg_delay()
980 return 0; in reg_delay()
983 #define NV_SETUP_RX_RING 0x01
984 #define NV_SETUP_TX_RING 0x02
993 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ in dma_high()
1047 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) in using_multi_irqs()
1048 return 0; in using_multi_irqs()
1119 writel(0, base + NvRegMSIIrqMask); in nv_disable_hw_interrupts()
1120 writel(0, base + NvRegIrqMask); in nv_disable_hw_interrupts()
1164 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, in mii_rw()
1169 retval = 0; in mii_rw()
1183 unsigned int tries = 0; in phy_reset()
1200 return 0; in phy_reset()
1219 for (i = 0; i < ARRAY_SIZE(ri); i++) { in init_realtek_8211b()
1224 return 0; in init_realtek_8211b()
1259 return 0; in init_realtek_8211c()
1275 return 0; in init_realtek_8201()
1298 return 0; in init_realtek_8201_cross()
1322 return 0; in init_cicada()
1384 return 0; in init_vitesse()
1460 np->gigabit = 0; in phy_init()
1529 return 0; in phy_init()
1564 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, in nv_stop_rx()
1571 writel(0, base + NvRegLinkSpeed); in nv_stop_rx()
1598 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, in nv_stop_tx()
1650 writel(0, base + NvRegMacReset); in nv_mac_reset()
1865 return 0; in nv_alloc_rx()
1907 return 0; in nv_alloc_rx_optimized()
1935 for (i = 0; i < np->rx_ring_size; i++) { in nv_init_rx()
1937 np->rx_ring.orig[i].flaglen = 0; in nv_init_rx()
1938 np->rx_ring.orig[i].buf = 0; in nv_init_rx()
1940 np->rx_ring.ex[i].flaglen = 0; in nv_init_rx()
1941 np->rx_ring.ex[i].txvlan = 0; in nv_init_rx()
1942 np->rx_ring.ex[i].bufhigh = 0; in nv_init_rx()
1943 np->rx_ring.ex[i].buflow = 0; in nv_init_rx()
1946 np->rx_skb[i].dma = 0; in nv_init_rx()
1966 np->tx_pkts_in_progress = 0; in nv_init_tx()
1969 np->tx_stop = 0; in nv_init_tx()
1971 for (i = 0; i < np->tx_ring_size; i++) { in nv_init_tx()
1973 np->tx_ring.orig[i].flaglen = 0; in nv_init_tx()
1974 np->tx_ring.orig[i].buf = 0; in nv_init_tx()
1976 np->tx_ring.ex[i].flaglen = 0; in nv_init_tx()
1977 np->tx_ring.ex[i].txvlan = 0; in nv_init_tx()
1978 np->tx_ring.ex[i].bufhigh = 0; in nv_init_tx()
1979 np->tx_ring.ex[i].buflow = 0; in nv_init_tx()
1982 np->tx_skb[i].dma = 0; in nv_init_tx()
1983 np->tx_skb[i].dma_len = 0; in nv_init_tx()
1984 np->tx_skb[i].dma_single = 0; in nv_init_tx()
2014 tx_skb->dma = 0; in nv_unmap_txskb()
2026 return 0; in nv_release_txskb()
2034 for (i = 0; i < np->tx_ring_size; i++) { in nv_drain_tx()
2036 np->tx_ring.orig[i].flaglen = 0; in nv_drain_tx()
2037 np->tx_ring.orig[i].buf = 0; in nv_drain_tx()
2039 np->tx_ring.ex[i].flaglen = 0; in nv_drain_tx()
2040 np->tx_ring.ex[i].txvlan = 0; in nv_drain_tx()
2041 np->tx_ring.ex[i].bufhigh = 0; in nv_drain_tx()
2042 np->tx_ring.ex[i].buflow = 0; in nv_drain_tx()
2049 np->tx_skb[i].dma = 0; in nv_drain_tx()
2050 np->tx_skb[i].dma_len = 0; in nv_drain_tx()
2051 np->tx_skb[i].dma_single = 0; in nv_drain_tx()
2055 np->tx_pkts_in_progress = 0; in nv_drain_tx()
2065 for (i = 0; i < np->rx_ring_size; i++) { in nv_drain_rx()
2067 np->rx_ring.orig[i].flaglen = 0; in nv_drain_rx()
2068 np->rx_ring.orig[i].buf = 0; in nv_drain_rx()
2070 np->rx_ring.ex[i].flaglen = 0; in nv_drain_rx()
2071 np->rx_ring.ex[i].txvlan = 0; in nv_drain_rx()
2072 np->rx_ring.ex[i].bufhigh = 0; in nv_drain_rx()
2073 np->rx_ring.ex[i].buflow = 0; in nv_drain_rx()
2103 int tx_status = 0; in nv_legacybackoff_reseed()
2158 miniseed1 &= 0x0fff; in nv_gear_backoff_reseed()
2159 if (miniseed1 == 0) in nv_gear_backoff_reseed()
2160 miniseed1 = 0xabc; in nv_gear_backoff_reseed()
2163 miniseed2 &= 0x0fff; in nv_gear_backoff_reseed()
2164 if (miniseed2 == 0) in nv_gear_backoff_reseed()
2165 miniseed2 = 0xabc; in nv_gear_backoff_reseed()
2167 ((miniseed2 & 0xF00) >> 8) | in nv_gear_backoff_reseed()
2168 (miniseed2 & 0x0F0) | in nv_gear_backoff_reseed()
2169 ((miniseed2 & 0x00F) << 8); in nv_gear_backoff_reseed()
2172 miniseed3 &= 0x0fff; in nv_gear_backoff_reseed()
2173 if (miniseed3 == 0) in nv_gear_backoff_reseed()
2174 miniseed3 = 0xabc; in nv_gear_backoff_reseed()
2176 ((miniseed3 & 0xF00) >> 8) | in nv_gear_backoff_reseed()
2177 (miniseed3 & 0x0F0) | in nv_gear_backoff_reseed()
2178 ((miniseed3 & 0x00F) << 8); in nv_gear_backoff_reseed()
2184 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) in nv_gear_backoff_reseed()
2185 combinedSeed |= 0x08; in nv_gear_backoff_reseed()
2186 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) in nv_gear_backoff_reseed()
2187 combinedSeed |= 0x8000; in nv_gear_backoff_reseed()
2190 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); in nv_gear_backoff_reseed()
2200 temp |= main_seedset[seedset][i-1] & 0x3ff; in nv_gear_backoff_reseed()
2201 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); in nv_gear_backoff_reseed()
2213 u32 tx_flags = 0; in nv_start_xmit()
2217 u32 offset = 0; in nv_start_xmit()
2220 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit()
2231 for (i = 0; i < fragments; i++) { in nv_start_xmit()
2235 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit()
2288 for (i = 0; i < fragments; i++) { in nv_start_xmit()
2291 offset = 0; in nv_start_xmit()
2324 np->put_tx_ctx->dma_single = 0; in nv_start_xmit()
2357 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; in nv_start_xmit()
2387 u32 tx_flags = 0; in nv_start_xmit_optimized()
2391 u32 offset = 0; in nv_start_xmit_optimized()
2394 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit_optimized()
2406 for (i = 0; i < fragments; i++) { in nv_start_xmit_optimized()
2410 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit_optimized()
2466 for (i = 0; i < fragments; i++) { in nv_start_xmit_optimized()
2469 offset = 0; in nv_start_xmit_optimized()
2501 np->put_tx_ctx->dma_single = 0; in nv_start_xmit_optimized()
2535 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; in nv_start_xmit_optimized()
2542 start_tx->txvlan = 0; in nv_start_xmit_optimized()
2615 int tx_work = 0; in nv_tx_done()
2617 unsigned int bytes_compl = 0; in nv_tx_done()
2675 np->tx_stop = 0; in nv_tx_done()
2685 int tx_work = 0; in nv_tx_done_optimized()
2687 unsigned long bytes_cleaned = 0; in nv_tx_done_optimized()
2732 np->tx_stop = 0; in nv_tx_done_optimized()
2762 for (i = 0; i <= np->register_size; i += 32) { in nv_tx_timeout()
2767 readl(base + i + 0), readl(base + i + 4), in nv_tx_timeout()
2773 for (i = 0; i < np->tx_ring_size; i += 4) { in nv_tx_timeout()
2817 np->tx_limit = 0; /* prevent giving HW any limited pkts */ in nv_tx_timeout()
2818 np->tx_stop = 0; /* prevent waking tx queue */ in nv_tx_timeout()
2900 int rx_work = 0; in nv_rx_process()
2926 if (len < 0) { in nv_rx_process()
2953 if (len < 0) { in nv_rx_process()
3001 u32 vlanflags = 0; in nv_rx_process_optimized()
3002 int rx_work = 0; in nv_rx_process_optimized()
3027 if (len < 0) { in nv_rx_process_optimized()
3110 return 0; in nv_change_mtu()
3154 return 0; in nv_change_mtu()
3162 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + in nv_copy_mac_to_hw()
3164 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); in nv_copy_mac_to_hw()
3166 writel(mac[0], base + NvRegMacAddrA); in nv_copy_mac_to_hw()
3204 return 0; in nv_set_mac_address()
3219 memset(addr, 0, sizeof(addr)); in nv_set_multicast()
3220 memset(mask, 0, sizeof(mask)); in nv_set_multicast()
3231 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; in nv_set_multicast()
3233 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; in nv_set_multicast()
3243 alwaysOn[0] &= a; in nv_set_multicast()
3244 alwaysOff[0] &= ~a; in nv_set_multicast()
3249 addr[0] = alwaysOn[0]; in nv_set_multicast()
3251 mask[0] = alwaysOn[0] | alwaysOff[0]; in nv_set_multicast()
3254 mask[0] = NVREG_MCASTMASKA_NONE; in nv_set_multicast()
3258 addr[0] |= NVREG_MCASTADDRA_FORCE; in nv_set_multicast()
3262 writel(addr[0], base + NvRegMulticastAddrA); in nv_set_multicast()
3264 writel(mask[0], base + NvRegMulticastMaskA); in nv_set_multicast()
3323 phyreg &= ~(0x3FF00); in nv_force_linkspeed()
3324 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) in nv_force_linkspeed()
3326 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) in nv_force_linkspeed()
3328 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_force_linkspeed()
3335 if (np->duplex == 0) in nv_force_linkspeed()
3366 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_force_linkspeed()
3381 * The function returns 0 if there is no link partner and 1 if there is
3388 int adv = 0; in nv_update_linkspeed()
3389 int lpa = 0; in nv_update_linkspeed()
3395 int retval = 0; in nv_update_linkspeed()
3397 u32 txrxFlags = 0; in nv_update_linkspeed()
3421 newdup = 0; in nv_update_linkspeed()
3422 retval = 0; in nv_update_linkspeed()
3426 if (np->autoneg == 0) { in nv_update_linkspeed()
3432 newdup = 0; in nv_update_linkspeed()
3438 newdup = 0; in nv_update_linkspeed()
3447 newdup = 0; in nv_update_linkspeed()
3448 retval = 0; in nv_update_linkspeed()
3475 newdup = 0; in nv_update_linkspeed()
3481 newdup = 0; in nv_update_linkspeed()
3484 newdup = 0; in nv_update_linkspeed()
3506 phyreg &= ~(0x3FF00); in nv_update_linkspeed()
3507 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || in nv_update_linkspeed()
3508 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) in nv_update_linkspeed()
3510 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3517 if (np->duplex == 0) in nv_update_linkspeed()
3557 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_update_linkspeed()
3563 pause_flags = 0; in nv_update_linkspeed()
3565 if (netif_running(dev) && (np->duplex != 0)) { in nv_update_linkspeed()
3646 writel(0, base + NvRegMSIIrqMask); in nv_msi_workaround()
3658 np->quiet_count = 0; in nv_change_interrupt_mode()
3676 return 0; in nv_change_interrupt_mode()
3701 writel(0, base + NvRegIrqMask); in nv_nic_irq()
3734 writel(0, base + NvRegIrqMask); in nv_nic_irq_optimized()
3750 for (i = 0;; i++) { in nv_nic_irq_tx()
3789 int rx_count, tx_work = 0, rx_work = 0; in nv_napi_poll()
3808 } while (retcode == 0 && in nv_napi_poll()
3809 rx_count > 0 && (rx_work += rx_count) < budget); in nv_napi_poll()
3862 for (i = 0;; i++) { in nv_nic_irq_rx()
3907 for (i = 0;; i++) { in nv_nic_irq_other()
3981 return IRQ_RETVAL(0); in nv_nic_irq_test()
3996 u32 msixmap = 0; in set_msix_vector_map()
4002 for (i = 0; i < 8; i++) { in set_msix_vector_map()
4003 if ((irqmask >> i) & 0x1) in set_msix_vector_map()
4008 msixmap = 0; in set_msix_vector_map()
4009 for (i = 0; i < 8; i++) { in set_msix_vector_map()
4010 if ((irqmask >> (i + 8)) & 0x1) in set_msix_vector_map()
4034 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_request_irq()
4040 if (ret > 0) { in nv_request_irq()
4080 writel(0, base + NvRegMSIXMap0); in nv_request_irq()
4081 writel(0, base + NvRegMSIXMap1); in nv_request_irq()
4098 /* map interrupts to vector 0 */ in nv_request_irq()
4099 writel(0, base + NvRegMSIXMap0); in nv_request_irq()
4100 writel(0, base + NvRegMSIXMap1); in nv_request_irq()
4103 return 0; in nv_request_irq()
4108 if (ret == 0) { in nv_request_irq()
4119 /* map interrupts to vector 0 */ in nv_request_irq()
4120 writel(0, base + NvRegMSIMap0); in nv_request_irq()
4121 writel(0, base + NvRegMSIMap1); in nv_request_irq()
4122 /* enable msi vector 0 */ in nv_request_irq()
4125 return 0; in nv_request_irq()
4129 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) in nv_request_irq()
4132 return 0; in nv_request_irq()
4147 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_free_irq()
4165 u32 mask = 0; in nv_do_nic_poll()
4167 unsigned int irq = 0; in nv_do_nic_poll()
4200 np->recover_error = 0; in nv_do_nic_poll()
4245 np->nic_poll_irq = 0; in nv_do_nic_poll()
4247 nv_nic_irq_optimized(0, dev); in nv_do_nic_poll()
4249 nv_nic_irq(0, dev); in nv_do_nic_poll()
4253 nv_nic_irq_rx(0, dev); in nv_do_nic_poll()
4257 nv_nic_irq_tx(0, dev); in nv_do_nic_poll()
4261 nv_nic_irq_other(0, dev); in nv_do_nic_poll()
4319 u32 flags = 0; in nv_set_wol()
4321 if (wolinfo->wolopts == 0) { in nv_set_wol()
4322 np->wolenabled = 0; in nv_set_wol()
4333 return 0; in nv_set_wol()
4414 return 0; in nv_get_link_ksettings()
4442 if ((advertising & mask) == 0) in nv_set_link_ksettings()
4530 np->autoneg = 0; in nv_set_link_ksettings()
4587 return 0; in nv_set_link_ksettings()
4607 for (i = 0; i < np->register_size/sizeof(u32); i++) in nv_get_regs()
4651 ret = 0; in nv_nway_reset()
4679 ring->rx_mini_pending != 0 || in nv_set_ringparam()
4680 ring->rx_jumbo_pending != 0 || in nv_set_ringparam()
4761 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); in nv_set_ringparam()
4762 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); in nv_set_ringparam()
4789 return 0; in nv_set_ringparam()
4798 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; in nv_get_pauseparam()
4799 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; in nv_get_pauseparam()
4800 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; in nv_get_pauseparam()
4808 if ((!np->autoneg && np->duplex == 0) || in nv_set_pauseparam()
4809 (np->autoneg && !pause->autoneg && np->duplex == 0)) { in nv_set_pauseparam()
4870 return 0; in nv_set_pauseparam()
4878 int err, retval = 0; in nv_set_loopback()
4886 return 0; in nv_set_loopback()
4912 return 0; in nv_set_loopback()
4968 if (retval != 0) in nv_set_features()
4989 return 0; in nv_set_features()
5010 return 0; in nv_get_sset_count()
5040 return 0; in nv_link_test()
5048 int i = 0; in nv_register_test()
5062 return 0; in nv_register_test()
5068 } while (nv_registers_test[++i].reg != 0); in nv_register_test()
5079 u32 save_msi_flags, save_poll_interval = 0; in nv_interrupt_test()
5088 np->intr_test = 0; in nv_interrupt_test()
5093 np->msi_flags |= 0x001; /* setup 1 vector */ in nv_interrupt_test()
5095 return 0; in nv_interrupt_test()
5129 if (nv_request_irq(dev, 0)) in nv_interrupt_test()
5130 return 0; in nv_interrupt_test()
5146 u32 filter_flags = 0; in nv_loopback_test()
5147 u32 misc1_flags = 0; in nv_loopback_test()
5180 ret = 0; in nv_loopback_test()
5192 for (i = 0; i < pkt_len; i++) in nv_loopback_test()
5193 pkt_data[i] = (u8)(i & 0xff); in nv_loopback_test()
5196 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); in nv_loopback_test()
5197 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5199 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); in nv_loopback_test()
5200 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); in nv_loopback_test()
5201 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5210 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); in nv_loopback_test()
5211 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); in nv_loopback_test()
5214 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); in nv_loopback_test()
5215 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); in nv_loopback_test()
5219 ret = 0; in nv_loopback_test()
5222 ret = 0; in nv_loopback_test()
5225 ret = 0; in nv_loopback_test()
5230 ret = 0; in nv_loopback_test()
5232 rx_skb = np->rx_skb[0].skb; in nv_loopback_test()
5233 for (i = 0; i < pkt_len; i++) { in nv_loopback_test()
5234 if (rx_skb->data[i] != (u8)(i & 0xff)) { in nv_loopback_test()
5235 ret = 0; in nv_loopback_test()
5269 memset(buffer, 0, count * sizeof(u64)); in nv_self_test()
5273 buffer[0] = 1; in nv_self_test()
5308 if (result == 0) { in nv_self_test()
5383 for (i = 0; i < 10; i++) { in nv_mgmt_acquire_sema()
5391 return 0; in nv_mgmt_acquire_sema()
5393 for (i = 0; i < 2; i++) { in nv_mgmt_acquire_sema()
5408 return 0; in nv_mgmt_acquire_sema()
5432 u32 data_ready2 = 0; in nv_mgmt_get_version()
5434 int ready = 0; in nv_mgmt_get_version()
5449 return 0; in nv_mgmt_get_version()
5473 writel(0, base + NvRegMulticastAddrB); in nv_open()
5476 writel(0, base + NvRegPacketFilterFlags); in nv_open()
5478 writel(0, base + NvRegTransmitterControl); in nv_open()
5479 writel(0, base + NvRegReceiverControl); in nv_open()
5481 writel(0, base + NvRegAdapterControl); in nv_open()
5490 writel(0, base + NvRegLinkSpeed); in nv_open()
5493 writel(0, base + NvRegUnknownSetupReg6); in nv_open()
5495 np->in_shutdown = 0; in nv_open()
5517 writel(0, base + NvRegMIIMask); in nv_open()
5549 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); in nv_open()
5559 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) in nv_open()
5572 if (nv_request_irq(dev, 0)) in nv_open()
5580 writel(0, base + NvRegMulticastAddrB); in nv_open()
5592 np->linkspeed = 0; in nv_open()
5620 return 0; in nv_open()
5643 nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */ in nv_close()
5671 return 0; in nv_close()
5716 u32 phystate_orig = 0, phystate; in nv_probe()
5717 int phyinitialized = 0; in nv_probe()
5744 timer_setup(&np->oom_kick, nv_do_rx_refill, 0); in nv_probe()
5745 timer_setup(&np->nic_poll, nv_do_nic_poll, 0); in nv_probe()
5755 if (err < 0) in nv_probe()
5766 addr = 0; in nv_probe()
5767 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { in nv_probe()
5820 np->vlanctl_bits = 0; in nv_probe()
5889 np->orig_mac[0] = readl(base + NvRegMacAddrA); in nv_probe()
5896 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5897 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5898 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5899 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5900 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5901 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5904 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5905 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5906 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5907 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5908 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5909 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5915 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + in nv_probe()
5917 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); in nv_probe()
5920 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5921 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5922 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5923 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5924 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5925 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5949 writel(0, base + NvRegWakeUpFlags); in nv_probe()
5950 np->wolenabled = 0; in nv_probe()
5959 pci_dev->revision >= 0xA3) in nv_probe()
5969 np->msi_flags = 0; in nv_probe()
5977 #if 0 in nv_probe()
5985 np->msi_flags |= 0x0001; in nv_probe()
5996 np->msi_flags |= 0x0003; in nv_probe()
6005 np->need_linktimer = 0; in nv_probe()
6012 pci_dev->revision >= 0xA2) in nv_probe()
6013 np->tx_limit = 0; in nv_probe()
6017 writel(0, base + NvRegMIIMask); in nv_probe()
6033 if (np->mgmt_version > 0) in nv_probe()
6050 int phyaddr = i & 0x1F; in nv_probe()
6055 if (id1 < 0 || id1 == 0xffff) in nv_probe()
6060 if (id2 < 0 || id2 == 0xffff) in nv_probe()
6095 np->duplex = 0; in nv_probe()
6110 nv_update_pause(dev, 0); in nv_probe()
6117 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", in nv_probe()
6138 return 0; in nv_probe()
6190 writel(np->orig_mac[0], base + NvRegMacAddrA); in nv_restore_mac_addr()
6235 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_suspend()
6238 return 0; in nv_suspend()
6247 int i, rc = 0; in nv_resume()
6250 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_resume()
6307 PCI_DEVICE(0x10DE, 0x01C3),
6311 PCI_DEVICE(0x10DE, 0x0066),
6315 PCI_DEVICE(0x10DE, 0x00D6),
6319 PCI_DEVICE(0x10DE, 0x0086),
6323 PCI_DEVICE(0x10DE, 0x008C),
6327 PCI_DEVICE(0x10DE, 0x00E6),
6331 PCI_DEVICE(0x10DE, 0x00DF),
6335 PCI_DEVICE(0x10DE, 0x0056),
6339 PCI_DEVICE(0x10DE, 0x0057),
6343 PCI_DEVICE(0x10DE, 0x0037),
6347 PCI_DEVICE(0x10DE, 0x0038),
6351 PCI_DEVICE(0x10DE, 0x0268),
6355 PCI_DEVICE(0x10DE, 0x0269),
6359 PCI_DEVICE(0x10DE, 0x0372),
6363 PCI_DEVICE(0x10DE, 0x0373),
6367 PCI_DEVICE(0x10DE, 0x03E5),
6371 PCI_DEVICE(0x10DE, 0x03E6),
6375 PCI_DEVICE(0x10DE, 0x03EE),
6379 PCI_DEVICE(0x10DE, 0x03EF),
6383 PCI_DEVICE(0x10DE, 0x0450),
6387 PCI_DEVICE(0x10DE, 0x0451),
6391 PCI_DEVICE(0x10DE, 0x0452),
6395 PCI_DEVICE(0x10DE, 0x0453),
6399 PCI_DEVICE(0x10DE, 0x054C),
6403 PCI_DEVICE(0x10DE, 0x054D),
6407 PCI_DEVICE(0x10DE, 0x054E),
6411 PCI_DEVICE(0x10DE, 0x054F),
6415 PCI_DEVICE(0x10DE, 0x07DC),
6419 PCI_DEVICE(0x10DE, 0x07DD),
6423 PCI_DEVICE(0x10DE, 0x07DE),
6427 PCI_DEVICE(0x10DE, 0x07DF),
6431 PCI_DEVICE(0x10DE, 0x0760),
6435 PCI_DEVICE(0x10DE, 0x0761),
6439 PCI_DEVICE(0x10DE, 0x0762),
6443 PCI_DEVICE(0x10DE, 0x0763),
6447 PCI_DEVICE(0x10DE, 0x0AB0),
6451 PCI_DEVICE(0x10DE, 0x0AB1),
6455 PCI_DEVICE(0x10DE, 0x0AB2),
6459 PCI_DEVICE(0x10DE, 0x0AB3),
6463 PCI_DEVICE(0x10DE, 0x0D7D),
6466 {0,},
6478 module_param(max_interrupt_work, int, 0);
6480 module_param(optimization_mode, int, 0);
6481 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an …
6482 module_param(poll_interval, int, 0);
6483 …imer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6484 module_param(msi, int, 0);
6485 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6486 module_param(msix, int, 0);
6487 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6488 module_param(dma_64bit, int, 0);
6489 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6490 module_param(phy_cross, int, 0);
6491 …rossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6492 module_param(phy_power_down, int, 0);
6493 …_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6494 module_param(debug_tx_timeout, bool, 0);