293 		&channel->common_reg->set_msix_mask_vect[msix_id%4]);  in vxge_hw_channel_msix_mask()
311 		&channel->common_reg->clear_msix_mask_vect[msix_id%4]);  in vxge_hw_channel_msix_unmask()
328 		&channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);  in vxge_hw_channel_msix_clear()
381 			writeq(val64, &hldev->common_reg->tim_int_status0);  in vxge_hw_device_intr_enable()
383 			writeq(~val64, &hldev->common_reg->tim_int_mask0);  in vxge_hw_device_intr_enable()
391 					&hldev->common_reg->tim_int_status1);  in vxge_hw_device_intr_enable()
394 					&hldev->common_reg->tim_int_mask1);  in vxge_hw_device_intr_enable()
398 	val64 = readq(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_intr_enable()
418 	writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);  in vxge_hw_device_intr_disable()
420 		&hldev->common_reg->tim_int_mask1);  in vxge_hw_device_intr_disable()
448 				&hldev->common_reg->titan_mask_all_int);  in vxge_hw_device_mask_all()
467 			&hldev->common_reg->titan_mask_all_int);  in vxge_hw_device_unmask_all()
480 	readl(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_flush_io()
888 	val64 = readq(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_begin_irq()
899 		adapter_status = readq(&hldev->common_reg->adapter_status);  in vxge_hw_device_begin_irq()
972 				&hldev->common_reg->tim_int_status0);  in vxge_hw_device_clear_tx_rx()
980 				&hldev->common_reg->tim_int_status1);  in vxge_hw_device_clear_tx_rx()
2217 		&hldev->common_reg->set_msix_mask_vect[msix_id % 4]);  in vxge_hw_vpath_msix_mask()
2239 			&hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);  in vxge_hw_vpath_msix_clear()
2243 			&hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);  in vxge_hw_vpath_msix_clear()
2264 			&hldev->common_reg->clear_msix_mask_vect[msix_id%4]);  in vxge_hw_vpath_msix_unmask()
2285 	val64 = readq(&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_mask_tx_rx()
2291 			&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_mask_tx_rx()
2294 	val64 = readl(&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_mask_tx_rx()
2301 			&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_mask_tx_rx()
2323 	val64 = readq(&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_unmask_tx_rx()
2329 			&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_unmask_tx_rx()
2337 			&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_unmask_tx_rx()
2387 			readl(&ring->common_reg->titan_general_int_status);  in vxge_hw_vpath_poll_rx()