490 		if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||  in mlx4_QUERY_FUNC_CAP_wrapper()
831 	dev_cap->flags2 = 0;  in mlx4_QUERY_DEV_CAP()
883 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;  in mlx4_QUERY_DEV_CAP()
885 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;  in mlx4_QUERY_DEV_CAP()
888 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;  in mlx4_QUERY_DEV_CAP()
902 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;  in mlx4_QUERY_DEV_CAP()
905 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;  in mlx4_QUERY_DEV_CAP()
908 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;  in mlx4_QUERY_DEV_CAP()
911 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;  in mlx4_QUERY_DEV_CAP()
914 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;  in mlx4_QUERY_DEV_CAP()
919 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;  in mlx4_QUERY_DEV_CAP()
922 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;  in mlx4_QUERY_DEV_CAP()
927 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;  in mlx4_QUERY_DEV_CAP()
960 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN;  in mlx4_QUERY_DEV_CAP()
963 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP;  in mlx4_QUERY_DEV_CAP()
1012 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;  in mlx4_QUERY_DEV_CAP()
1014 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;  in mlx4_QUERY_DEV_CAP()
1016 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1018 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1022 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;  in mlx4_QUERY_DEV_CAP()
1024 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;  in mlx4_QUERY_DEV_CAP()
1027 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;  in mlx4_QUERY_DEV_CAP()
1029 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;  in mlx4_QUERY_DEV_CAP()
1032 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;  in mlx4_QUERY_DEV_CAP()
1034 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;  in mlx4_QUERY_DEV_CAP()
1040 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;  in mlx4_QUERY_DEV_CAP()
1042 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;  in mlx4_QUERY_DEV_CAP()
1044 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;  in mlx4_QUERY_DEV_CAP()
1047 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;  in mlx4_QUERY_DEV_CAP()
1050 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;  in mlx4_QUERY_DEV_CAP()
1053 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;  in mlx4_QUERY_DEV_CAP()
1055 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;  in mlx4_QUERY_DEV_CAP()
1065 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;  in mlx4_QUERY_DEV_CAP()
1077 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;  in mlx4_QUERY_DEV_CAP()
1091 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;  in mlx4_QUERY_DEV_CAP()
1093 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;  in mlx4_QUERY_DEV_CAP()
1095 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;  in mlx4_QUERY_DEV_CAP()
1097 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;  in mlx4_QUERY_DEV_CAP()
1099 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;  in mlx4_QUERY_DEV_CAP()
1101 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;  in mlx4_QUERY_DEV_CAP()
1103 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SW_CQ_INIT;  in mlx4_QUERY_DEV_CAP()
1120 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;  in mlx4_QUERY_DEV_CAP()
1171 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {  in mlx4_dev_cap_dump()
1180 	dump_dev_cap_flags2(dev, dev_cap->flags2);  in mlx4_dev_cap_dump()
1918 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)  in mlx4_INIT_HCA()
1948 	if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&  in mlx4_INIT_HCA()
1949 	    (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {  in mlx4_INIT_HCA()
1961 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)  in mlx4_INIT_HCA()
1964 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW) {  in mlx4_INIT_HCA()
2050 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {  in mlx4_INIT_HCA()
2485 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))  in mlx4_config_dev_retrieval()
2841 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))  in mlx4_config_mad_demux()
3033 	context->flags2 |=  SET_PORT_GEN_PHV_VALID;  in mlx4_SET_PORT_phv_bit()
3066 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&  in set_phv_bit()
3067 	    !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {  in set_phv_bit()