209 	u8 field;  in mlx4_QUERY_FUNC()  local
235 	MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);  in mlx4_QUERY_FUNC()
236 	func->bus = field & 0xf;  in mlx4_QUERY_FUNC()
237 	MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);  in mlx4_QUERY_FUNC()
238 	func->device = field & 0xf1;  in mlx4_QUERY_FUNC()
239 	MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);  in mlx4_QUERY_FUNC()
240 	func->function = field & 0x7;  in mlx4_QUERY_FUNC()
241 	MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);  in mlx4_QUERY_FUNC()
242 	func->physical_function = field & 0xf;  in mlx4_QUERY_FUNC()
247 	MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);  in mlx4_QUERY_FUNC()
248 	func->rsvd_uars = field & 0x0f;  in mlx4_QUERY_FUNC()
332 	u8	field, port;  in mlx4_QUERY_FUNC_CAP_wrapper()  local
406 		field = vhcr->in_modifier -  in mlx4_QUERY_FUNC_CAP_wrapper()
408 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
414 		field  = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;  in mlx4_QUERY_FUNC_CAP_wrapper()
418 			field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;  in mlx4_QUERY_FUNC_CAP_wrapper()
422 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
443 		field = 0;  in mlx4_QUERY_FUNC_CAP_wrapper()
445 			field |= QUERY_FUNC_CAP_PHV_BIT;  in mlx4_QUERY_FUNC_CAP_wrapper()
447 			field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE;  in mlx4_QUERY_FUNC_CAP_wrapper()
448 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
459 		field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |  in mlx4_QUERY_FUNC_CAP_wrapper()
462 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
464 		field = min(  in mlx4_QUERY_FUNC_CAP_wrapper()
467 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
472 		field = 0; /* protected FMR support not available as yet */  in mlx4_QUERY_FUNC_CAP_wrapper()
473 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);  in mlx4_QUERY_FUNC_CAP_wrapper()
544 	u8			field, op_modifier;  in mlx4_QUERY_FUNC_CAP()  local
568 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);  in mlx4_QUERY_FUNC_CAP()
569 		if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {  in mlx4_QUERY_FUNC_CAP()
574 		func_cap->flags = field;  in mlx4_QUERY_FUNC_CAP()
577 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);  in mlx4_QUERY_FUNC_CAP()
578 		func_cap->num_ports = field;  in mlx4_QUERY_FUNC_CAP()
670 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);  in mlx4_QUERY_FUNC_CAP()
671 		if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {  in mlx4_QUERY_FUNC_CAP()
678 	MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);  in mlx4_QUERY_FUNC_CAP()
679 	func_cap->physical_port = field;  in mlx4_QUERY_FUNC_CAP()
729 	u8 field;  in mlx4_QUERY_DEV_CAP()  local
844 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
845 	dev_cap->reserved_qps = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
846 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
847 	dev_cap->max_qps = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
848 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
849 	dev_cap->reserved_srqs = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
850 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
851 	dev_cap->max_srqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
852 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
853 	dev_cap->max_cq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
854 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
855 	dev_cap->reserved_cqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
856 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
857 	dev_cap->max_cqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
858 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);  in mlx4_QUERY_DEV_CAP()
859 	dev_cap->max_mpts = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
860 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
861 	dev_cap->reserved_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
862 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
863 	dev_cap->max_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
864 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);  in mlx4_QUERY_DEV_CAP()
865 	dev_cap->reserved_mtts = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
866 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);  in mlx4_QUERY_DEV_CAP()
867 	dev_cap->reserved_mrws = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
870 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
871 	dev_cap->max_requester_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
872 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
873 	dev_cap->max_responder_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
874 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);  in mlx4_QUERY_DEV_CAP()
875 	field &= 0x1f;  in mlx4_QUERY_DEV_CAP()
876 	if (!field)  in mlx4_QUERY_DEV_CAP()
879 		dev_cap->max_gso_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
881 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);  in mlx4_QUERY_DEV_CAP()
882 	if (field & 0x20)  in mlx4_QUERY_DEV_CAP()
884 	if (field & 0x10)  in mlx4_QUERY_DEV_CAP()
886 	field &= 0xf;  in mlx4_QUERY_DEV_CAP()
887 	if (field) {  in mlx4_QUERY_DEV_CAP()
889 		dev_cap->max_rss_tbl_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
892 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);  in mlx4_QUERY_DEV_CAP()
893 	dev_cap->max_rdma_global = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
894 	MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);  in mlx4_QUERY_DEV_CAP()
895 	dev_cap->local_ca_ack_delay = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
896 	MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);  in mlx4_QUERY_DEV_CAP()
897 	dev_cap->num_ports = field & 0xf;  in mlx4_QUERY_DEV_CAP()
898 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
899 	dev_cap->max_msg_sz = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
900 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);  in mlx4_QUERY_DEV_CAP()
901 	if (field & 0x10)  in mlx4_QUERY_DEV_CAP()
903 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);  in mlx4_QUERY_DEV_CAP()
904 	if (field & 0x80)  in mlx4_QUERY_DEV_CAP()
906 	dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
907 	if (field & 0x20)  in mlx4_QUERY_DEV_CAP()
909 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);  in mlx4_QUERY_DEV_CAP()
910 	if (field & 0x80)  in mlx4_QUERY_DEV_CAP()
912 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);  in mlx4_QUERY_DEV_CAP()
913 	if (field & 0x80)  in mlx4_QUERY_DEV_CAP()
915 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
916 	dev_cap->fs_max_num_qp_per_entry = field;  in mlx4_QUERY_DEV_CAP()
917 	MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET);  in mlx4_QUERY_DEV_CAP()
918 	if (field & (1 << 5))  in mlx4_QUERY_DEV_CAP()
920 	MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);  in mlx4_QUERY_DEV_CAP()
921 	if (field & 0x1)  in mlx4_QUERY_DEV_CAP()
925 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);  in mlx4_QUERY_DEV_CAP()
926 	if (field & 0x80)  in mlx4_QUERY_DEV_CAP()
931 	MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET);  in mlx4_QUERY_DEV_CAP()
932 	dev_cap->wol_port[1] = !!(field & 0x20);  in mlx4_QUERY_DEV_CAP()
933 	dev_cap->wol_port[2] = !!(field & 0x40);  in mlx4_QUERY_DEV_CAP()
934 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);  in mlx4_QUERY_DEV_CAP()
935 	dev_cap->reserved_uars = field >> 4;  in mlx4_QUERY_DEV_CAP()
936 	MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
937 	dev_cap->uar_size = 1 << ((field & 0x3f) + 20);  in mlx4_QUERY_DEV_CAP()
938 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
939 	dev_cap->min_page_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
941 	MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);  in mlx4_QUERY_DEV_CAP()
942 	if (field & 0x80) {  in mlx4_QUERY_DEV_CAP()
943 		MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
944 		dev_cap->bf_reg_size = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
945 		MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);  in mlx4_QUERY_DEV_CAP()
946 		if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))  in mlx4_QUERY_DEV_CAP()
947 			field = 3;  in mlx4_QUERY_DEV_CAP()
948 		dev_cap->bf_regs_per_page = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
953 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
954 	dev_cap->max_sq_sg = field;  in mlx4_QUERY_DEV_CAP()
958 	MLX4_GET(field, outbox, QUERY_DEV_CAP_USER_MAC_EN_OFFSET);  in mlx4_QUERY_DEV_CAP()
959 	if (field & (1 << 2))  in mlx4_QUERY_DEV_CAP()
961 	MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET);  in mlx4_QUERY_DEV_CAP()
962 	if (field & 0x1)  in mlx4_QUERY_DEV_CAP()
964 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);  in mlx4_QUERY_DEV_CAP()
965 	dev_cap->max_qp_per_mcg = 1 << field;  in mlx4_QUERY_DEV_CAP()
966 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);  in mlx4_QUERY_DEV_CAP()
967 	dev_cap->reserved_mgms = field & 0xf;  in mlx4_QUERY_DEV_CAP()
968 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);  in mlx4_QUERY_DEV_CAP()
969 	dev_cap->max_mcgs = 1 << field;  in mlx4_QUERY_DEV_CAP()
970 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);  in mlx4_QUERY_DEV_CAP()
971 	dev_cap->reserved_pds = field >> 4;  in mlx4_QUERY_DEV_CAP()
972 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);  in mlx4_QUERY_DEV_CAP()
973 	dev_cap->max_pds = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
974 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);  in mlx4_QUERY_DEV_CAP()
975 	dev_cap->reserved_xrcds = field >> 4;  in mlx4_QUERY_DEV_CAP()
976 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);  in mlx4_QUERY_DEV_CAP()
977 	dev_cap->max_xrcds = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
1000 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
1001 	dev_cap->max_srq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1002 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);  in mlx4_QUERY_DEV_CAP()
1003 	dev_cap->max_qp_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1004 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
1005 	dev_cap->resize_srq = field & 1;  in mlx4_QUERY_DEV_CAP()
1006 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);  in mlx4_QUERY_DEV_CAP()
1007 	dev_cap->max_rq_sg = field;  in mlx4_QUERY_DEV_CAP()
1010 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);  in mlx4_QUERY_DEV_CAP()
1011 	if (field & (1 << 4))  in mlx4_QUERY_DEV_CAP()
1013 	if (field & (1 << 5))  in mlx4_QUERY_DEV_CAP()
1015 	if (field & (1 << 6))  in mlx4_QUERY_DEV_CAP()
1017 	if (field & (1 << 7))  in mlx4_QUERY_DEV_CAP()
1025 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);  in mlx4_QUERY_DEV_CAP()
1026 	if (field & 0x20)  in mlx4_QUERY_DEV_CAP()
1028 	if (field & (1 << 2))  in mlx4_QUERY_DEV_CAP()
1030 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);  in mlx4_QUERY_DEV_CAP()
1031 	if (field & 0x80)  in mlx4_QUERY_DEV_CAP()
1033 	if (field & 0x40)  in mlx4_QUERY_DEV_CAP()
1048 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);  in mlx4_QUERY_DEV_CAP()
1049 	if (field & 1<<6)  in mlx4_QUERY_DEV_CAP()
1051 	MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);  in mlx4_QUERY_DEV_CAP()
1052 	if (field & 1<<3)  in mlx4_QUERY_DEV_CAP()
1054 	if (field & (1 << 5))  in mlx4_QUERY_DEV_CAP()
1187 	u8 field;  in mlx4_QUERY_PORT()  local
1204 		MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);  in mlx4_QUERY_PORT()
1205 		port_cap->max_vl	   = field >> 4;  in mlx4_QUERY_PORT()
1206 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);  in mlx4_QUERY_PORT()
1207 		port_cap->ib_mtu	   = field >> 4;  in mlx4_QUERY_PORT()
1208 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1209 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);  in mlx4_QUERY_PORT()
1210 		port_cap->max_gids	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1211 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);  in mlx4_QUERY_PORT()
1212 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1231 		MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);  in mlx4_QUERY_PORT()
1232 		port_cap->link_state = (field & 0x80) >> 7;  in mlx4_QUERY_PORT()
1233 		port_cap->supported_port_types = field & 3;  in mlx4_QUERY_PORT()
1234 		port_cap->suggested_type = (field >> 3) & 1;  in mlx4_QUERY_PORT()
1235 		port_cap->default_sense = (field >> 4) & 1;  in mlx4_QUERY_PORT()
1236 		port_cap->dmfs_optimized_state = (field >> 5) & 1;  in mlx4_QUERY_PORT()
1237 		MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);  in mlx4_QUERY_PORT()
1238 		port_cap->ib_mtu	   = field & 0xf;  in mlx4_QUERY_PORT()
1239 		MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);  in mlx4_QUERY_PORT()
1240 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1241 		MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);  in mlx4_QUERY_PORT()
1242 		port_cap->max_gids	   = 1 << (field >> 4);  in mlx4_QUERY_PORT()
1243 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1244 		MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);  in mlx4_QUERY_PORT()
1245 		port_cap->max_vl	   = field & 0xf;  in mlx4_QUERY_PORT()
1246 		port_cap->max_tc_eth	   = field >> 4;  in mlx4_QUERY_PORT()
1247 		MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);  in mlx4_QUERY_PORT()
1248 		port_cap->log_max_macs  = field & 0xf;  in mlx4_QUERY_PORT()
1249 		port_cap->log_max_vlans = field >> 4;  in mlx4_QUERY_PORT()
1277 	u8	field;  in mlx4_QUERY_DEV_CAP_wrapper()  local
1315 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1316 	field &= ~0x0F;  in mlx4_QUERY_DEV_CAP_wrapper()
1317 	field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;  in mlx4_QUERY_DEV_CAP_wrapper()
1318 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1321 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1322 	field &= 0x7f;  in mlx4_QUERY_DEV_CAP_wrapper()
1323 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1326 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);  in mlx4_QUERY_DEV_CAP_wrapper()
1327 	field &= 0xd7;  in mlx4_QUERY_DEV_CAP_wrapper()
1328 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);  in mlx4_QUERY_DEV_CAP_wrapper()
1331 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1332 	field &= 0x7f;  in mlx4_QUERY_DEV_CAP_wrapper()
1333 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1336 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1337 	field &= 0x7f;  in mlx4_QUERY_DEV_CAP_wrapper()
1338 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1348 		MLX4_GET(field, outbox->buf,  in mlx4_QUERY_DEV_CAP_wrapper()
1350 		field &= 0x7f;  in mlx4_QUERY_DEV_CAP_wrapper()
1351 		MLX4_PUT(outbox->buf, field,  in mlx4_QUERY_DEV_CAP_wrapper()
1356 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1357 	field &= ~0x80;  in mlx4_QUERY_DEV_CAP_wrapper()
1358 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1367 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1368 	field &= 0xfe;  in mlx4_QUERY_DEV_CAP_wrapper()
1369 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1376 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);  in mlx4_QUERY_DEV_CAP_wrapper()
1377 	field &= 0xef;  in mlx4_QUERY_DEV_CAP_wrapper()
1378 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);  in mlx4_QUERY_DEV_CAP_wrapper()
1381 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1382 	field &= 0xfb;  in mlx4_QUERY_DEV_CAP_wrapper()
1383 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);  in mlx4_QUERY_DEV_CAP_wrapper()
1489 	u16			field;  in mlx4_get_slave_pkey_gid_tbl_len()  local
1504 	MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);  in mlx4_get_slave_pkey_gid_tbl_len()
1505 	*gid_tbl_len = field;  in mlx4_get_slave_pkey_gid_tbl_len()
1507 	MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);  in mlx4_get_slave_pkey_gid_tbl_len()
1508 	*pkey_tbl_len = field;  in mlx4_get_slave_pkey_gid_tbl_len()
2299 	u16 field;  in mlx4_INIT_PORT()  local
2326 		field = 128 << dev->caps.ib_mtu_cap[port];  in mlx4_INIT_PORT()
2327 		MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);  in mlx4_INIT_PORT()
2328 		field = dev->caps.gid_table_len[port];  in mlx4_INIT_PORT()
2329 		MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);  in mlx4_INIT_PORT()
2330 		field = dev->caps.pkey_table_len[port];  in mlx4_INIT_PORT()
2331 		MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);  in mlx4_INIT_PORT()