Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
43 PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
54 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
62 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
64 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
105 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
108 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
109 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
114 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
117 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
118 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
119 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
122 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
131 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
141 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
144 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
157 /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
163 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
166 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
167 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
168 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
169 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
171 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
173 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
174 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
188 /* Yukon-Optima */
197 PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */
198 PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */
199 PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */
202 PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */
204 PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */
208 /* Yukon-Supreme */
213 PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */
220 PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */
227 PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */
228 …PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ …
230 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
234 PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
236 PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */
238 PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */
239 PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */
240 PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */
241 PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */
265 /* Special ISR registers (Yukon-2 only) */
308 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
310 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
368 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
369 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
370 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
371 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
372 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
373 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
374 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
375 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
376 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
377 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
391 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
393 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
419 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
423 Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
424 Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
425 Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
429 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
451 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
452 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
469 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
470 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
475 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
482 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
509 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
515 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
523 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
537 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
538 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
539 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
540 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
541 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
542 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
543 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
544 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
545 CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
546 CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */
547 CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
558 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
559 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
560 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
590 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
602 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
612 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
620 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
641 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
677 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
679 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
683 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
688 * Bank 4 - 5
739 /* Yukon-2 */
760 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
765 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
791 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
792 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
793 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
794 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
795 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
837 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
838 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
839 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
840 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
843 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
845 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
847 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
854 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
855 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
862 /* Rx BMU Control / Status Registers (Yukon-2) */
865 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
866 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
868 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
869 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
870 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
871 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
872 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
875 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
876 BMU_START = 1<<8, /* Start Rx/Tx Queue */
879 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
883 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
894 /* Tx BMU Control / Status Registers (Yukon-2) */
895 /* Bit 31: same as for Rx */
897 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
905 TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
906 TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */
908 TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */
910 TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */
938 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
952 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
953 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
954 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
955 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
965 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
967 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
988 /* Threshold values for Yukon-EC Ultra and Extreme */
1010 /* Polling Unit Registers (Yukon-2 only) */
1037 /* ASF Subsystem Registers (Yukon-2 only) */
1051 /* Status BMU Registers (Yukon-2 only)*/
1065 /* FIFO Control/Status Registers (Yukon-2 only)*/
1074 /* Level and ISR Timer Registers (Yukon-2 only)*/
1106 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
1135 * Marvel-PHY Registers, indirect addressed over GMAC
1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1144 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1147 /* Marvel-specific registers */
1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1149 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1177 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1179 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1182 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1189 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1190 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1191 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1198 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1200 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1222 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1223 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1224 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1225 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1226 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1238 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1239 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1240 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1241 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1249 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1250 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1262 /** Marvell-Specific */
1270 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1271 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1272 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1273 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1274 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1282 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1283 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1297 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1299 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1307 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1311 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1330 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1333 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1336 PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
1341 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1342 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1344 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1351 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1369 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1383 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1387 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1408 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1409 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1418 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1420 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1422 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1423 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1427 PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1442 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1471 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1523 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1537 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1547 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1593 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1594 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1597 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1605 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1610 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1612 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1636 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1655 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1656 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1660 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1661 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1674 * MIB Counters base address definitions (low word) -
1682 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1690 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1691 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1692 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1693 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1694 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1695 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1696 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1697 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1698 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1700 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1708 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1709 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1710 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1711 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1712 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1713 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1728 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1738 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1744 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1745 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1746 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1747 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1748 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1749 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1750 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1754 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1756 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1757 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1758 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1765 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1776 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1777 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1778 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1805 GM_SMOD_VLAN_ENA = 1<<9, /* Enable VLAN (Max. Frame Len) */
1806 GM_SMOD_JUMBO_ENA = 1<<8, /* Enable Jumbo (Max. Frame Len) */
1808 GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */
1810 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1840 GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1847 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1848 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1854 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1862 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1864 RX_GCLKMAC_ENA = 1<<31, /* RX MAC Clock Gating Enable */
1867 RX_STFW_DIS = 1<<29, /* RX Store and Forward Enable */
1870 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1872 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1880 GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
1882 GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
1892 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1893 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1894 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1895 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1907 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1909 RX_IPV6_SA_MOB_ENA = 1<<9, /* IPv6 SA Mobility Support Enable */
1911 RX_IPV6_DA_MOB_ENA = 1<<7, /* IPv6 DA Mobility Support Enable */
1913 RX_PTR_SYNCDLY_ENA = 1<<5, /* Pointers Delay Synch Enable */
1915 RX_ASF_NEWFLAG_ENA = 1<<3, /* RX ASF Flag New Logic Enable */
1916 RX_ASF_NEWFLAG_DIS = 1<<2, /* RX ASF Flag New Logic Disable */
1917 RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
1918 RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
1923 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1929 TX_STFW_ENA = 1<<30,/* Enable Store & Forward */
1931 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1934 TX_PCI_JUM_ENA = 1<<23,/* PCI Jumbo Mode enable */
1935 TX_PCI_JUM_DIS = 1<<22,/* PCI Jumbo Mode enable */
2004 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2009 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
2017 GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
2018 GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
2037 GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
2053 GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
2055 GPC_PAUSE = 1<<9, /* Pause enable */
2139 /* YUKON-2 STATUS opcodes defines */
2311 return !(hw->flags & SKY2_HW_FIBRE_PHY); in sky2_is_copper()
2317 return readl(hw->regs + reg); in sky2_read32()
2322 return readw(hw->regs + reg); in sky2_read16()
2327 return readb(hw->regs + reg); in sky2_read8()
2332 writel(val, hw->regs + reg); in sky2_write32()
2337 writew(val, hw->regs + reg); in sky2_write16()
2342 writeb(val, hw->regs + reg); in sky2_write8()
2347 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))