Lines Matching refs:mvpp2_write
74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
410 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
412 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
416 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
435 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
544 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
626 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); in mvpp2_bm_init()
628 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); in mvpp2_bm_init()
676 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
697 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
1098 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
1109 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
1117 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_enable()
1125 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_disable()
1535 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_read_index()
1918 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
1920 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
1923 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); in mvpp2_defaults_set()
1927 mvpp2_write(port->priv, in mvpp2_defaults_set()
1933 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
1939 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
1941 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
1944 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
1954 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
1971 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
1984 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
2006 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
2007 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
2020 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
2024 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
2069 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
2099 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
2317 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
2323 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
2332 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
2344 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
2419 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
2435 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); in mvpp2_tx_time_coal_set()
2556 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); in mvpp2_aggr_txq_init()
2557 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), in mvpp2_aggr_txq_init()
2584 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
2700 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
2758 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
2764 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
2767 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
2831 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); in mvpp2_txq_deinit()
2901 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
2912 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4092 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
5453 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), in mvpp2_rx_irqs_setup()
5467 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); in mvpp2_rx_irqs_setup()
5471 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); in mvpp2_rx_irqs_setup()
6563 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); in mvpp2_conf_mbus_windows()
6564 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); in mvpp2_conf_mbus_windows()
6567 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); in mvpp2_conf_mbus_windows()
6575 mvpp2_write(priv, MVPP2_WIN_BASE(i), in mvpp2_conf_mbus_windows()
6579 mvpp2_write(priv, MVPP2_WIN_SIZE(i), in mvpp2_conf_mbus_windows()
6585 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); in mvpp2_conf_mbus_windows()
6594 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
6596 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
6600 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, in mvpp2_rx_fifo_init()
6602 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); in mvpp2_rx_fifo_init()
6616 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), in mvpp22_rx_fifo_init()
6618 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), in mvpp22_rx_fifo_init()
6621 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), in mvpp22_rx_fifo_init()
6623 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), in mvpp22_rx_fifo_init()
6627 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp22_rx_fifo_init()
6629 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp22_rx_fifo_init()
6633 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, in mvpp22_rx_fifo_init()
6635 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); in mvpp22_rx_fifo_init()
6654 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); in mvpp22_tx_fifo_init()
6655 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); in mvpp22_tx_fifo_init()
6663 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); in mvpp2_axi_init()
6678 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); in mvpp2_axi_init()
6679 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); in mvpp2_axi_init()
6682 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
6683 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
6684 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
6685 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
6688 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); in mvpp2_axi_init()
6689 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); in mvpp2_axi_init()
6695 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); in mvpp2_axi_init()
6696 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); in mvpp2_axi_init()
6703 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); in mvpp2_axi_init()
6710 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); in mvpp2_axi_init()
6767 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); in mvpp2_init()