Lines Matching refs:mvpp2_read

79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)  in mvpp2_read()  function
414 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_create()
512 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & in mvpp2_check_hw_buf_num()
514 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & in mvpp2_check_hw_buf_num()
542 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_destroy()
673 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
694 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
1536 return mvpp2_read(priv, reg); in mvpp2_read_index()
1715 *pstats++ += mvpp2_read(port->priv, in mvpp2_read_stats()
1935 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
1951 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
1969 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
1982 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
2021 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
2042 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
2052 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
2092 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
2320 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
2326 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
2336 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
2544 aggr_txq->next_desc_to_proc = mvpp2_read(priv, in mvpp2_aggr_txq_init()
2760 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
2897 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()