Lines Matching +full:0 +full:x00004000
19 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
20 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
38 if (0) \
40 } while (0)
46 #define PCI_DCSR_MRRS 0x59
47 #define PCI_DCSR_MRRS_MASK 0x70
50 MRRS_128B = 0x00,
51 MRRS_256B = 0x10,
52 MRRS_512B = 0x20,
53 MRRS_1024B = 0x30,
54 MRRS_2048B = 0x40,
55 MRRS_4096B = 0x50,
58 #define PCI_SPI 0xB0
61 SPI_EN = 0x10,
62 SPI_MISO = 0x08,
63 SPI_MOSI = 0x04,
64 SPI_SCLK = 0x02,
65 SPI_CS = 0x01,
85 SPI_MODE_CPHA = 0x01,
86 SPI_MODE_CPOL = 0x02,
87 SPI_MODE_DUP = 0x80,
92 #define PCI_PRIV_PE1 0xE4
95 PE1_ASPMSUPRT = 0x00000003, /*
97 * Aspm_support[1:0]
100 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
101 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
102 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
103 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
104 PE1_GPREG0 = 0x0000FF00, /*
109 * [4:0] Reserved
111 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
112 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
113 PE1_REVID = 0xFF000000, /* RO: Rev ID */
117 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
118 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
119 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
120 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
127 PCC_OFF = 0,
132 PCC_OFF_TO = 0,
137 PCC_OFF_CNT = 0,
227 TXFLAG_OWN = 0x80,
228 TXFLAG_INT = 0x40,
229 TXFLAG_64BIT = 0x20,
230 TXFLAG_TCPCS = 0x10,
231 TXFLAG_UDPCS = 0x08,
232 TXFLAG_IPCS = 0x04,
233 TXFLAG_LSEN = 0x02,
234 TXFLAG_TAGON = 0x01,
239 TXWBFLAG_OWN = 0x80,
240 TXWBFLAG_INT = 0x40,
241 TXWBFLAG_TMOUT = 0x20,
242 TXWBFLAG_TRYOUT = 0x10,
243 TXWBFLAG_COL = 0x08,
305 RXFLAG_OWN = 0x80,
306 RXFLAG_INT = 0x40,
307 RXFLAG_64BIT = 0x20,
311 RXWBFLAG_OWN = 0x8000,
312 RXWBFLAG_INT = 0x4000,
313 RXWBFLAG_MF = 0x2000,
314 RXWBFLAG_64BIT = 0x2000,
315 RXWBFLAG_TCPON = 0x1000,
316 RXWBFLAG_UDPON = 0x0800,
317 RXWBFLAG_IPCS = 0x0400,
318 RXWBFLAG_TCPCS = 0x0200,
319 RXWBFLAG_UDPCS = 0x0100,
320 RXWBFLAG_TAGON = 0x0080,
321 RXWBFLAG_IPV4 = 0x0040,
322 RXWBFLAG_IPV6 = 0x0020,
323 RXWBFLAG_PAUSE = 0x0010,
324 RXWBFLAG_MAGIC = 0x0008,
325 RXWBFLAG_WAKEUP = 0x0004,
326 RXWBFLAG_DEST = 0x0003,
327 RXWBFLAG_DEST_UNI = 0x0001,
328 RXWBFLAG_DEST_MUL = 0x0002,
329 RXWBFLAG_DEST_BRO = 0x0003,
333 RXWBDCNT_WBCPL = 0x80,
334 RXWBDCNT_DCNT = 0x7F,
338 RXWBERR_LIMIT = 0x80,
339 RXWBERR_MIIER = 0x40,
340 RXWBERR_NIBON = 0x20,
341 RXWBERR_COLON = 0x10,
342 RXWBERR_ABORT = 0x08,
343 RXWBERR_SHORT = 0x04,
344 RXWBERR_OVERUN = 0x02,
345 RXWBERR_CRCERR = 0x01,
346 RXWBERR_ALLERR = 0xFF,
458 #define JME_REG_LEN 0x500
473 JME_MAC = 0x0000,
474 JME_PHY = 0x0400,
475 JME_MISC = 0x0800,
476 JME_RSS = 0x0C00,
480 JME_MAC_LEN = 0x80,
481 JME_PHY_LEN = 0x58,
482 JME_MISC_LEN = 0x98,
483 JME_RSS_LEN = 0xFF,
487 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
488 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
489 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
490 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
491 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
492 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
493 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
494 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
496 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
497 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
498 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
499 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
500 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
501 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
502 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
503 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
504 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
505 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
506 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
507 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
509 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
510 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
511 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
514 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
515 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
516 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
517 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
518 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
521 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
522 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
523 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
524 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
525 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
526 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
527 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
528 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
529 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
530 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
531 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
532 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
533 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
534 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
535 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
536 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
543 TXCS_QUEUE7S = 0x00008000,
544 TXCS_QUEUE6S = 0x00004000,
545 TXCS_QUEUE5S = 0x00002000,
546 TXCS_QUEUE4S = 0x00001000,
547 TXCS_QUEUE3S = 0x00000800,
548 TXCS_QUEUE2S = 0x00000400,
549 TXCS_QUEUE1S = 0x00000200,
550 TXCS_QUEUE0S = 0x00000100,
551 TXCS_FIFOTH = 0x000000C0,
552 TXCS_DMASIZE = 0x00000030,
553 TXCS_BURST = 0x00000004,
554 TXCS_ENABLE = 0x00000001,
558 TXCS_FIFOTH_16QW = 0x000000C0,
559 TXCS_FIFOTH_12QW = 0x00000080,
560 TXCS_FIFOTH_8QW = 0x00000040,
561 TXCS_FIFOTH_4QW = 0x00000000,
563 TXCS_DMASIZE_64B = 0x00000000,
564 TXCS_DMASIZE_128B = 0x00000010,
565 TXCS_DMASIZE_256B = 0x00000020,
566 TXCS_DMASIZE_512B = 0x00000030,
568 TXCS_SELECT_QUEUE0 = 0x00000000,
569 TXCS_SELECT_QUEUE1 = 0x00010000,
570 TXCS_SELECT_QUEUE2 = 0x00020000,
571 TXCS_SELECT_QUEUE3 = 0x00030000,
572 TXCS_SELECT_QUEUE4 = 0x00040000,
573 TXCS_SELECT_QUEUE5 = 0x00050000,
574 TXCS_SELECT_QUEUE6 = 0x00060000,
575 TXCS_SELECT_QUEUE7 = 0x00070000,
587 TXMCS_IFG2 = 0xC0000000,
588 TXMCS_IFG1 = 0x30000000,
589 TXMCS_TTHOLD = 0x00000300,
590 TXMCS_FBURST = 0x00000080,
591 TXMCS_CARRIEREXT = 0x00000040,
592 TXMCS_DEFER = 0x00000020,
593 TXMCS_BACKOFF = 0x00000010,
594 TXMCS_CARRIERSENSE = 0x00000008,
595 TXMCS_COLLISION = 0x00000004,
596 TXMCS_CRC = 0x00000002,
597 TXMCS_PADDING = 0x00000001,
601 TXMCS_IFG2_6_4 = 0x00000000,
602 TXMCS_IFG2_8_5 = 0x40000000,
603 TXMCS_IFG2_10_6 = 0x80000000,
604 TXMCS_IFG2_12_7 = 0xC0000000,
606 TXMCS_IFG1_8_4 = 0x00000000,
607 TXMCS_IFG1_12_6 = 0x10000000,
608 TXMCS_IFG1_16_8 = 0x20000000,
609 TXMCS_IFG1_20_10 = 0x30000000,
611 TXMCS_TTHOLD_1_8 = 0x00000000,
612 TXMCS_TTHOLD_1_4 = 0x00000100,
613 TXMCS_TTHOLD_1_2 = 0x00000200,
614 TXMCS_TTHOLD_FULL = 0x00000300,
625 TXPFC_VLAN_TAG = 0xFFFF0000,
626 TXPFC_VLAN_EN = 0x00008000,
627 TXPFC_PF_EN = 0x00000001,
631 TXTRHD_TXPEN = 0x80000000,
632 TXTRHD_TXP = 0x7FFFFF00,
633 TXTRHD_TXREN = 0x00000080,
634 TXTRHD_TXRL = 0x0000007F,
639 TXTRHD_TXRL_SHIFT = 0,
643 TXTRHD_FULLDUPLEX = 0x00000000,
645 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
655 RXCS_FIFOTHTP = 0x30000000,
657 RXCS_FIFOTHNP = 0x0C000000,
658 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
659 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
660 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
661 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
662 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
663 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
664 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
665 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
666 RXCS_QST = 0x00000004, /* Receive queue start */
667 RXCS_SUSPEND = 0x00000002,
668 RXCS_ENABLE = 0x00000001,
672 RXCS_FIFOTHTP_16T = 0x00000000,
673 RXCS_FIFOTHTP_32T = 0x10000000,
674 RXCS_FIFOTHTP_64T = 0x20000000,
675 RXCS_FIFOTHTP_128T = 0x30000000,
677 RXCS_FIFOTHNP_16QW = 0x00000000,
678 RXCS_FIFOTHNP_32QW = 0x04000000,
679 RXCS_FIFOTHNP_64QW = 0x08000000,
680 RXCS_FIFOTHNP_128QW = 0x0C000000,
682 RXCS_DMAREQSZ_16B = 0x00000000,
683 RXCS_DMAREQSZ_32B = 0x01000000,
684 RXCS_DMAREQSZ_64B = 0x02000000,
685 RXCS_DMAREQSZ_128B = 0x03000000,
687 RXCS_QUEUESEL_Q0 = 0x00000000,
688 RXCS_QUEUESEL_Q1 = 0x00010000,
689 RXCS_QUEUESEL_Q2 = 0x00020000,
690 RXCS_QUEUESEL_Q3 = 0x00030000,
692 RXCS_RETRYGAP_256ns = 0x00000000,
693 RXCS_RETRYGAP_512ns = 0x00001000,
694 RXCS_RETRYGAP_1024ns = 0x00002000,
695 RXCS_RETRYGAP_2048ns = 0x00003000,
696 RXCS_RETRYGAP_4096ns = 0x00004000,
697 RXCS_RETRYGAP_8192ns = 0x00005000,
698 RXCS_RETRYGAP_16384ns = 0x00006000,
699 RXCS_RETRYGAP_32768ns = 0x00007000,
701 RXCS_RETRYCNT_0 = 0x00000000,
702 RXCS_RETRYCNT_4 = 0x00000100,
703 RXCS_RETRYCNT_8 = 0x00000200,
704 RXCS_RETRYCNT_12 = 0x00000300,
705 RXCS_RETRYCNT_16 = 0x00000400,
706 RXCS_RETRYCNT_20 = 0x00000500,
707 RXCS_RETRYCNT_24 = 0x00000600,
708 RXCS_RETRYCNT_28 = 0x00000700,
709 RXCS_RETRYCNT_32 = 0x00000800,
710 RXCS_RETRYCNT_36 = 0x00000900,
711 RXCS_RETRYCNT_40 = 0x00000A00,
712 RXCS_RETRYCNT_44 = 0x00000B00,
713 RXCS_RETRYCNT_48 = 0x00000C00,
714 RXCS_RETRYCNT_52 = 0x00000D00,
715 RXCS_RETRYCNT_56 = 0x00000E00,
716 RXCS_RETRYCNT_60 = 0x00000F00,
731 RXMCS_ALLFRAME = 0x00000800,
732 RXMCS_BRDFRAME = 0x00000400,
733 RXMCS_MULFRAME = 0x00000200,
734 RXMCS_UNIFRAME = 0x00000100,
735 RXMCS_ALLMULFRAME = 0x00000080,
736 RXMCS_MULFILTERED = 0x00000040,
737 RXMCS_RXCOLLDEC = 0x00000020,
738 RXMCS_FLOWCTRL = 0x00000008,
739 RXMCS_VTAGRM = 0x00000004,
740 RXMCS_PREPAD = 0x00000002,
741 RXMCS_CHECKSUM = 0x00000001,
751 #define PHY_GAD_TEST_MODE_1 0x00002000
752 #define PHY_GAD_TEST_MODE_MSK 0x0000E000
753 #define JM_PHY_SPEC_REG_READ 0x00004000
754 #define JM_PHY_SPEC_REG_WRITE 0x00008000
756 #define JM_PHY_SPEC_ADDR_REG 0x1E
757 #define JM_PHY_SPEC_DATA_REG 0x1F
759 #define JM_PHY_EXT_COMM_0_REG 0x30
760 #define JM_PHY_EXT_COMM_1_REG 0x31
761 #define JM_PHY_EXT_COMM_2_REG 0x32
762 #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
763 #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
764 #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
765 #define PCI_PRIV_SHARE_NICCTRL 0xF5
766 #define JME_FLAG_PHYEA_ENABLE 0x2
775 WFOI_MASK_SEL = 0x00000070,
776 WFOI_CRC_SEL = 0x00000008,
777 WFOI_FRAME_SEL = 0x00000007,
788 SMI_DATA_MASK = 0xFFFF0000,
789 SMI_REG_ADDR_MASK = 0x0000F800,
790 SMI_PHY_ADDR_MASK = 0x000007C0,
791 SMI_OP_WRITE = 0x00000020,
792 /* Set to 1, after req done it'll be cleared to 0 */
793 SMI_OP_REQ = 0x00000010,
794 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
795 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
796 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
797 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
823 GHC_SWRST = 0x40000000,
824 GHC_TO_CLK_SRC = 0x00C00000,
825 GHC_TXMAC_CLK_SRC = 0x00300000,
826 GHC_DPX = 0x00000040,
827 GHC_SPEED = 0x00000030,
828 GHC_LINK_POLL = 0x00000001,
832 GHC_SPEED_10M = 0x00000010,
833 GHC_SPEED_100M = 0x00000020,
834 GHC_SPEED_1000M = 0x00000030,
838 GHC_TO_CLK_OFF = 0x00000000,
839 GHC_TO_CLK_GPHY = 0x00400000,
840 GHC_TO_CLK_PCIE = 0x00800000,
841 GHC_TO_CLK_INVALID = 0x00C00000,
845 GHC_TXMAC_CLK_OFF = 0x00000000,
846 GHC_TXMAC_CLK_GPHY = 0x00100000,
847 GHC_TXMAC_CLK_PCIE = 0x00200000,
848 GHC_TXMAC_CLK_INVALID = 0x00300000,
855 PMCS_STMASK = 0xFFFF0000,
856 PMCS_WF7DET = 0x80000000,
857 PMCS_WF6DET = 0x40000000,
858 PMCS_WF5DET = 0x20000000,
859 PMCS_WF4DET = 0x10000000,
860 PMCS_WF3DET = 0x08000000,
861 PMCS_WF2DET = 0x04000000,
862 PMCS_WF1DET = 0x02000000,
863 PMCS_WF0DET = 0x01000000,
864 PMCS_LFDET = 0x00040000,
865 PMCS_LRDET = 0x00020000,
866 PMCS_MFDET = 0x00010000,
867 PMCS_ENMASK = 0x0000FFFF,
868 PMCS_WF7EN = 0x00008000,
869 PMCS_WF6EN = 0x00004000,
870 PMCS_WF5EN = 0x00002000,
871 PMCS_WF4EN = 0x00001000,
872 PMCS_WF3EN = 0x00000800,
873 PMCS_WF2EN = 0x00000400,
874 PMCS_WF1EN = 0x00000200,
875 PMCS_WF0EN = 0x00000100,
876 PMCS_LFEN = 0x00000004,
877 PMCS_LREN = 0x00000002,
878 PMCS_MFEN = 0x00000001,
885 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
886 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
887 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
888 PHY_PWR_CLKSEL = 0x08000000, /*
891 * 0: xtl_out = phy_giga.A_XTL25_O
900 PHY_LINK_SPEED_MASK = 0x0000C000,
901 PHY_LINK_DUPLEX = 0x00002000,
902 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
903 PHY_LINK_UP = 0x00000400,
904 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
905 PHY_LINK_MDI_STAT = 0x00000040,
909 PHY_LINK_SPEED_10M = 0x00000000,
910 PHY_LINK_SPEED_100M = 0x00004000,
911 PHY_LINK_SPEED_1000M = 0x00008000,
920 SMBCSR_CNACK = 0x00020000,
921 SMBCSR_RELOAD = 0x00010000,
922 SMBCSR_EEPROMD = 0x00000020,
923 SMBCSR_INITDONE = 0x00000010,
924 SMBCSR_BUSY = 0x0000000F,
928 SMBINTF_HWDATR = 0xFF000000,
929 SMBINTF_HWDATW = 0x00FF0000,
930 SMBINTF_HWADDR = 0x0000FF00,
931 SMBINTF_HWRWN = 0x00000020,
932 SMBINTF_HWCMD = 0x00000010,
933 SMBINTF_FASTM = 0x00000008,
934 SMBINTF_GPIOSCL = 0x00000004,
935 SMBINTF_GPIOSDA = 0x00000002,
936 SMBINTF_GPIOEN = 0x00000001,
940 SMBINTF_HWRWN_READ = 0x00000020,
941 SMBINTF_HWRWN_WRITE = 0x00000000,
953 #define JME_EEPROM_MAGIC 0x250
959 TMCSR_SWIT = 0x80000000,
960 TMCSR_EN = 0x01000000,
961 TMCSR_CNT = 0x00FFFFFF,
965 * General Purpose REG-0
968 GPREG0_DISSH = 0xFF000000,
969 GPREG0_PCIRLMT = 0x00300000,
970 GPREG0_PCCNOMUTCLR = 0x00040000,
971 GPREG0_LNKINTPOLL = 0x00001000,
972 GPREG0_PCCTMR = 0x00000300,
973 GPREG0_PHYADDR = 0x0000001F,
977 GPREG0_DISSH_DW7 = 0x80000000,
978 GPREG0_DISSH_DW6 = 0x40000000,
979 GPREG0_DISSH_DW5 = 0x20000000,
980 GPREG0_DISSH_DW4 = 0x10000000,
981 GPREG0_DISSH_DW3 = 0x08000000,
982 GPREG0_DISSH_DW2 = 0x04000000,
983 GPREG0_DISSH_DW1 = 0x02000000,
984 GPREG0_DISSH_DW0 = 0x01000000,
985 GPREG0_DISSH_ALL = 0xFF000000,
987 GPREG0_PCIRLMT_8 = 0x00000000,
988 GPREG0_PCIRLMT_6 = 0x00100000,
989 GPREG0_PCIRLMT_5 = 0x00200000,
990 GPREG0_PCIRLMT_4 = 0x00300000,
992 GPREG0_PCCTMR_16ns = 0x00000000,
993 GPREG0_PCCTMR_256ns = 0x00000100,
994 GPREG0_PCCTMR_1us = 0x00000200,
995 GPREG0_PCCTMR_1ms = 0x00000300,
997 GPREG0_PHYADDR_1 = 0x00000001,
1008 GPREG1_RXCLKOFF = 0x04000000,
1009 GPREG1_PCREQN = 0x00020000,
1010 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1011 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1012 GPREG1_INTRDELAYUNIT = 0x00000018,
1013 GPREG1_INTRDELAYENABLE = 0x00000007,
1017 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1018 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1019 GPREG1_INTDLYUNIT_1US = 0x00000010,
1020 GPREG1_INTDLYUNIT_16US = 0x00000018,
1022 GPREG1_INTDLYEN_1U = 0x00000001,
1023 GPREG1_INTDLYEN_2U = 0x00000002,
1024 GPREG1_INTDLYEN_3U = 0x00000003,
1025 GPREG1_INTDLYEN_4U = 0x00000004,
1026 GPREG1_INTDLYEN_5U = 0x00000005,
1027 GPREG1_INTDLYEN_6U = 0x00000006,
1028 GPREG1_INTDLYEN_7U = 0x00000007,
1037 INTR_SWINTR = 0x80000000,
1038 INTR_TMINTR = 0x40000000,
1039 INTR_LINKCH = 0x20000000,
1040 INTR_PAUSERCV = 0x10000000,
1041 INTR_MAGICRCV = 0x08000000,
1042 INTR_WAKERCV = 0x04000000,
1043 INTR_PCCRX0TO = 0x02000000,
1044 INTR_PCCRX1TO = 0x01000000,
1045 INTR_PCCRX2TO = 0x00800000,
1046 INTR_PCCRX3TO = 0x00400000,
1047 INTR_PCCTXTO = 0x00200000,
1048 INTR_PCCRX0 = 0x00100000,
1049 INTR_PCCRX1 = 0x00080000,
1050 INTR_PCCRX2 = 0x00040000,
1051 INTR_PCCRX3 = 0x00020000,
1052 INTR_PCCTX = 0x00010000,
1053 INTR_RX3EMP = 0x00008000,
1054 INTR_RX2EMP = 0x00004000,
1055 INTR_RX1EMP = 0x00002000,
1056 INTR_RX0EMP = 0x00001000,
1057 INTR_RX3 = 0x00000800,
1058 INTR_RX2 = 0x00000400,
1059 INTR_RX1 = 0x00000200,
1060 INTR_RX0 = 0x00000100,
1061 INTR_TX7 = 0x00000080,
1062 INTR_TX6 = 0x00000040,
1063 INTR_TX5 = 0x00000020,
1064 INTR_TX4 = 0x00000010,
1065 INTR_TX3 = 0x00000008,
1066 INTR_TX2 = 0x00000004,
1067 INTR_TX1 = 0x00000002,
1068 INTR_TX0 = 0x00000001,
1084 PCCRXTO_MASK = 0xFFFF0000,
1085 PCCRX_MASK = 0x0000FF00,
1089 PCCTXTO_MASK = 0xFFFF0000,
1090 PCCTX_MASK = 0x0000FF00,
1091 PCCTX_QS_MASK = 0x000000FF,
1105 PCCTXQ0_EN = 0x00000001,
1106 PCCTXQ1_EN = 0x00000002,
1107 PCCTXQ2_EN = 0x00000004,
1108 PCCTXQ3_EN = 0x00000008,
1109 PCCTXQ4_EN = 0x00000010,
1110 PCCTXQ5_EN = 0x00000020,
1111 PCCTXQ6_EN = 0x00000040,
1112 PCCTXQ7_EN = 0x00000080,
1119 CM_FPGAVER_MASK = 0xFFFF0000,
1120 CM_CHIPREV_MASK = 0x0000FF00,
1121 CM_CHIPMODE_MASK = 0x0000000F,
1133 JME_APMC_PCIE_SD_EN = 0x40000000,
1134 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1135 JME_APMC_EPIEN = 0x04000000,
1136 JME_APMC_EPIEN_CTRL = 0x03000000,
1140 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1141 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1178 switch (reg & 0xF00) { in reg_dbg()
1179 case 0x000: in reg_dbg()
1180 regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; in reg_dbg()
1182 case 0x400: in reg_dbg()
1183 regname = PE_REG_NAME[(reg & 0xFF) >> 2]; in reg_dbg()
1185 case 0x800: in reg_dbg()
1186 regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; in reg_dbg()
1189 regname = PE_REG_NAME[0]; in reg_dbg()
1229 PREG17_SPEED = 0xC000,
1230 PREG17_DUPLEX = 0x2000,
1231 PREG17_SPDRSV = 0x0800,
1232 PREG17_LNKUP = 0x0400,
1233 PREG17_MDI = 0x0040,
1237 PREG17_SPEED_10M = 0x0000,
1238 PREG17_SPEED_100M = 0x4000,
1239 PREG17_SPEED_1000M = 0x8000,
1242 #define BMSR_ANCOMP 0x0020
1249 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; in is_buggy250()