Lines Matching refs:reg_idx

200 	u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx));  in ixgbevf_get_tx_pending()
201 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
385 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
386 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1370 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1373 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1696 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1699 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1702 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1703 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
1704 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(reg_idx), in ixgbevf_configure_tx_ring()
1708 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(reg_idx), 0); in ixgbevf_configure_tx_ring()
1709 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(reg_idx), 0); in ixgbevf_configure_tx_ring()
1712 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(reg_idx), in ixgbevf_configure_tx_ring()
1717 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(reg_idx), 0); in ixgbevf_configure_tx_ring()
1718 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(reg_idx), 0); in ixgbevf_configure_tx_ring()
1719 ring->tail = adapter->io_addr + IXGBE_VFTDT(reg_idx); in ixgbevf_configure_tx_ring()
1742 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl); in ixgbevf_configure_tx_ring()
1747 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx)); in ixgbevf_configure_tx_ring()
1750 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); in ixgbevf_configure_tx_ring()
1812 u8 reg_idx = ring->reg_idx; in ixgbevf_disable_rx_queue() local
1816 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_disable_rx_queue()
1820 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); in ixgbevf_disable_rx_queue()
1825 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_disable_rx_queue()
1830 reg_idx); in ixgbevf_disable_rx_queue()
1839 u8 reg_idx = ring->reg_idx; in ixgbevf_rx_desc_queue_enable() local
1845 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_rx_desc_queue_enable()
1850 reg_idx); in ixgbevf_rx_desc_queue_enable()
1917 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_rx_ring() local
1920 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_configure_rx_ring()
1923 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(reg_idx), rdba & DMA_BIT_MASK(32)); in ixgbevf_configure_rx_ring()
1924 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(reg_idx), rdba >> 32); in ixgbevf_configure_rx_ring()
1925 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx), in ixgbevf_configure_rx_ring()
1930 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), in ixgbevf_configure_rx_ring()
1933 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), in ixgbevf_configure_rx_ring()
1939 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(reg_idx), 0); in ixgbevf_configure_rx_ring()
1940 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(reg_idx), 0); in ixgbevf_configure_rx_ring()
1941 ring->tail = adapter->io_addr + IXGBE_VFRDT(reg_idx); in ixgbevf_configure_rx_ring()
1956 ixgbevf_configure_srrctl(adapter, ring, reg_idx); in ixgbevf_configure_rx_ring()
1973 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); in ixgbevf_configure_rx_ring()
2200 adapter->tx_ring[0]->reg_idx = def_q; in ixgbevf_configure_dcb()
2503 u8 reg_idx = adapter->tx_ring[i]->reg_idx; in ixgbevf_down() local
2505 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), in ixgbevf_down()
2510 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; in ixgbevf_down() local
2512 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), in ixgbevf_down()
2711 int reg_idx = txr_idx + xdp_idx; in ixgbevf_alloc_q_vector() local
2748 ring->reg_idx = reg_idx; in ixgbevf_alloc_q_vector()
2756 reg_idx++; in ixgbevf_alloc_q_vector()
2776 ring->reg_idx = reg_idx; in ixgbevf_alloc_q_vector()
2785 reg_idx++; in ixgbevf_alloc_q_vector()
2805 ring->reg_idx = rxr_idx; in ixgbevf_alloc_q_vector()