Lines Matching +full:per +full:- +full:board
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
10 * @adapter: board private structure to initialize
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov()
32 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
35 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_dcb_sriov()
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
44 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
52 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
57 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
61 if (fcoe->offset < tcs) in ixgbe_cache_ring_dcb_sriov()
65 if (fcoe->indices) { in ixgbe_cache_ring_dcb_sriov()
66 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
69 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
70 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
71 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
72 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
73 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
77 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
78 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
79 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
80 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
89 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
93 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_get_first_reg_idx()
94 u8 num_tcs = adapter->hw_tcs; in ixgbe_get_first_reg_idx()
99 switch (hw->mac.type) { in ixgbe_get_first_reg_idx()
112 * TCs : TC0/1 TC2/3 TC4-7 in ixgbe_get_first_reg_idx()
141 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
142 * @adapter: board private structure to initialize
149 u8 num_tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb()
157 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_cache_ring_dcb()
162 adapter->tx_ring[offset + i]->reg_idx = tx_idx; in ixgbe_cache_ring_dcb()
163 adapter->rx_ring[offset + i]->reg_idx = rx_idx; in ixgbe_cache_ring_dcb()
164 adapter->rx_ring[offset + i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb()
165 adapter->tx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
166 adapter->rx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
175 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
176 * @adapter: board private structure to initialize
178 * SR-IOV doesn't use any descriptor rings but changes the default if
185 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_sriov()
187 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_sriov()
188 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS]; in ixgbe_cache_ring_sriov()
193 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)) in ixgbe_cache_ring_sriov()
196 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_sriov()
198 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
199 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
202 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
206 if ((reg_idx & ~vmdq->mask) >= rss->indices) { in ixgbe_cache_ring_sriov()
208 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
210 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
211 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_sriov()
216 for (; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
217 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
218 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_sriov()
222 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
223 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
226 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
230 if ((reg_idx & rss->mask) >= rss->indices) in ixgbe_cache_ring_sriov()
231 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
232 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
237 for (; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_sriov()
238 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
246 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
247 * @adapter: board private structure to initialize
256 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_rss()
257 adapter->rx_ring[i]->reg_idx = i; in ixgbe_cache_ring_rss()
258 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_rss()
260 for (i = 0, reg_idx = 0; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
261 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
262 for (i = 0; i < adapter->num_xdp_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
263 adapter->xdp_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
269 * ixgbe_cache_ring_register - Descriptor ring to register mapping
270 * @adapter: board private structure to initialize
272 * Once we know the feature-set enabled for the device, we'll cache
282 adapter->rx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
283 adapter->tx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
301 return adapter->xdp_prog ? nr_cpu_ids : 0; in ixgbe_xdp_queues()
313 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB
314 * @adapter: board private structure to initialize
316 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
324 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_dcb_sriov_queues()
329 u8 tcs = adapter->hw_tcs; in ixgbe_set_dcb_sriov_queues()
336 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_dcb_sriov_queues()
343 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
345 /* 16 pools w/ 8 TC per pool */ in ixgbe_set_dcb_sriov_queues()
349 /* 32 pools w/ 4 TC per pool */ in ixgbe_set_dcb_sriov_queues()
357 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i; in ixgbe_set_dcb_sriov_queues()
361 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
364 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_dcb_sriov_queues()
365 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_dcb_sriov_queues()
371 adapter->ring_feature[RING_F_RSS].indices = 1; in ixgbe_set_dcb_sriov_queues()
372 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; in ixgbe_set_dcb_sriov_queues()
375 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_sriov_queues()
377 adapter->num_rx_pools = vmdq_i; in ixgbe_set_dcb_sriov_queues()
378 adapter->num_rx_queues_per_pool = tcs; in ixgbe_set_dcb_sriov_queues()
380 adapter->num_tx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
381 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_sriov_queues()
382 adapter->num_rx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
385 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_sriov_queues()
388 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_sriov_queues()
391 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_dcb_sriov_queues()
395 fcoe->indices = fcoe_i; in ixgbe_set_dcb_sriov_queues()
396 fcoe->offset = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
399 adapter->num_tx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
400 adapter->num_rx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
403 fcoe->indices = 1; in ixgbe_set_dcb_sriov_queues()
404 fcoe->offset = ixgbe_fcoe_get_tc(adapter); in ixgbe_set_dcb_sriov_queues()
406 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; in ixgbe_set_dcb_sriov_queues()
408 fcoe->indices = 0; in ixgbe_set_dcb_sriov_queues()
409 fcoe->offset = 0; in ixgbe_set_dcb_sriov_queues()
416 netdev_set_tc_queue(adapter->netdev, i, 1, i); in ixgbe_set_dcb_sriov_queues()
423 struct net_device *dev = adapter->netdev; in ixgbe_set_dcb_queues()
429 tcs = adapter->hw_tcs; in ixgbe_set_dcb_queues()
436 rss_i = dev->num_tx_queues / tcs; in ixgbe_set_dcb_queues()
437 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { in ixgbe_set_dcb_queues()
438 /* 8 TC w/ 4 queues per TC */ in ixgbe_set_dcb_queues()
442 /* 8 TC w/ 8 queues per TC */ in ixgbe_set_dcb_queues()
446 /* 4 TC w/ 16 queues per TC */ in ixgbe_set_dcb_queues()
452 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_dcb_queues()
453 rss_i = min_t(int, rss_i, f->limit); in ixgbe_set_dcb_queues()
454 f->indices = rss_i; in ixgbe_set_dcb_queues()
455 f->mask = rss_m; in ixgbe_set_dcb_queues()
458 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_queues()
466 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_queues()
469 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_queues()
470 f->indices = min_t(u16, rss_i, f->limit); in ixgbe_set_dcb_queues()
471 f->offset = rss_i * tc; in ixgbe_set_dcb_queues()
478 adapter->num_tx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
479 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_queues()
480 adapter->num_rx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
487 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices
488 * @adapter: board private structure to initialize
490 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
497 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_sriov_queues()
499 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit; in ixgbe_set_sriov_queues()
505 /* only proceed if SR-IOV is enabled */ in ixgbe_set_sriov_queues()
506 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_sriov_queues()
513 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
518 /* 64 pool mode with 2 queues per pool */ in ixgbe_set_sriov_queues()
523 /* 32 pool mode with up to 4 queues per pool */ in ixgbe_set_sriov_queues()
533 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m)); in ixgbe_set_sriov_queues()
537 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
540 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_sriov_queues()
541 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_sriov_queues()
544 adapter->ring_feature[RING_F_RSS].indices = rss_i; in ixgbe_set_sriov_queues()
545 adapter->ring_feature[RING_F_RSS].mask = rss_m; in ixgbe_set_sriov_queues()
547 adapter->num_rx_pools = vmdq_i; in ixgbe_set_sriov_queues()
548 adapter->num_rx_queues_per_pool = rss_i; in ixgbe_set_sriov_queues()
550 adapter->num_rx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
551 adapter->num_tx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
552 adapter->num_xdp_queues = 0; in ixgbe_set_sriov_queues()
555 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_sriov_queues()
563 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_sriov_queues()
566 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_sriov_queues()
569 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
573 fcoe->indices = fcoe_i; in ixgbe_set_sriov_queues()
574 fcoe->offset = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
579 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_sriov_queues()
580 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_sriov_queues()
584 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
585 fcoe->offset = fcoe_i - fcoe->indices; in ixgbe_set_sriov_queues()
587 fcoe_i -= rss_i; in ixgbe_set_sriov_queues()
591 adapter->num_tx_queues += fcoe_i; in ixgbe_set_sriov_queues()
592 adapter->num_rx_queues += fcoe_i; in ixgbe_set_sriov_queues()
602 netdev_set_num_tc(adapter->netdev, 1); in ixgbe_set_sriov_queues()
605 netdev_set_tc_queue(adapter->netdev, 0, in ixgbe_set_sriov_queues()
606 adapter->num_rx_queues_per_pool, 0); in ixgbe_set_sriov_queues()
612 * ixgbe_set_rss_queues - Allocate queues for RSS
613 * @adapter: board private structure to initialize
616 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
621 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_set_rss_queues()
626 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_rss_queues()
627 rss_i = f->limit; in ixgbe_set_rss_queues()
629 f->indices = rss_i; in ixgbe_set_rss_queues()
631 if (hw->mac.type < ixgbe_mac_X550) in ixgbe_set_rss_queues()
632 f->mask = IXGBE_RSS_16Q_MASK; in ixgbe_set_rss_queues()
634 f->mask = IXGBE_RSS_64Q_MASK; in ixgbe_set_rss_queues()
637 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
644 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_set_rss_queues()
645 f = &adapter->ring_feature[RING_F_FDIR]; in ixgbe_set_rss_queues()
647 rss_i = f->indices = f->limit; in ixgbe_set_rss_queues()
649 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) in ixgbe_set_rss_queues()
650 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
662 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_rss_queues()
663 struct net_device *dev = adapter->netdev; in ixgbe_set_rss_queues()
666 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_rss_queues()
669 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); in ixgbe_set_rss_queues()
670 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); in ixgbe_set_rss_queues()
672 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_rss_queues()
673 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_rss_queues()
677 f->indices = min_t(u16, fcoe_i, f->limit); in ixgbe_set_rss_queues()
678 f->offset = fcoe_i - f->indices; in ixgbe_set_rss_queues()
683 adapter->num_rx_queues = rss_i; in ixgbe_set_rss_queues()
684 adapter->num_tx_queues = rss_i; in ixgbe_set_rss_queues()
685 adapter->num_xdp_queues = ixgbe_xdp_queues(adapter); in ixgbe_set_rss_queues()
691 * ixgbe_set_num_queues - Allocate queues for device, feature dependent
692 * @adapter: board private structure to initialize
704 adapter->num_rx_queues = 1; in ixgbe_set_num_queues()
705 adapter->num_tx_queues = 1; in ixgbe_set_num_queues()
706 adapter->num_xdp_queues = 0; in ixgbe_set_num_queues()
707 adapter->num_rx_pools = 1; in ixgbe_set_num_queues()
708 adapter->num_rx_queues_per_pool = 1; in ixgbe_set_num_queues()
725 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors
726 * @adapter: board private structure
728 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
729 * return a negative error code if unable to acquire MSI-X vectors for any
734 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_acquire_msix_vectors()
737 /* We start by asking for one vector per queue pair with XDP queues in ixgbe_acquire_msix_vectors()
740 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues); in ixgbe_acquire_msix_vectors()
741 vectors = max(vectors, adapter->num_xdp_queues); in ixgbe_acquire_msix_vectors()
743 /* It is easy to be greedy for MSI-X vectors. However, it really in ixgbe_acquire_msix_vectors()
750 /* Some vectors are necessary for non-queue interrupts */ in ixgbe_acquire_msix_vectors()
753 /* Hardware can only support a maximum of hw.mac->max_msix_vectors. in ixgbe_acquire_msix_vectors()
759 vectors = min_t(int, vectors, hw->mac.max_msix_vectors); in ixgbe_acquire_msix_vectors()
761 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0] in ixgbe_acquire_msix_vectors()
766 adapter->msix_entries = kcalloc(vectors, in ixgbe_acquire_msix_vectors()
769 if (!adapter->msix_entries) in ixgbe_acquire_msix_vectors()
770 return -ENOMEM; in ixgbe_acquire_msix_vectors()
773 adapter->msix_entries[i].entry = i; in ixgbe_acquire_msix_vectors()
775 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, in ixgbe_acquire_msix_vectors()
780 * acquiring within the specified range of MSI-X vectors in ixgbe_acquire_msix_vectors()
782 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n", in ixgbe_acquire_msix_vectors()
785 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
786 kfree(adapter->msix_entries); in ixgbe_acquire_msix_vectors()
787 adapter->msix_entries = NULL; in ixgbe_acquire_msix_vectors()
795 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
800 vectors -= NON_Q_VECTORS; in ixgbe_acquire_msix_vectors()
801 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors); in ixgbe_acquire_msix_vectors()
809 ring->next = head->ring; in ixgbe_add_ring()
810 head->ring = ring; in ixgbe_add_ring()
811 head->count++; in ixgbe_add_ring()
812 head->next_update = jiffies + 1; in ixgbe_add_ring()
816 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
817 * @adapter: board private structure to initialize
827 * We allocate one q_vector. If allocation fails we return -ENOMEM.
835 int node = dev_to_node(&adapter->pdev->dev); in ixgbe_alloc_q_vector()
838 int cpu = -1; in ixgbe_alloc_q_vector()
840 u8 tcs = adapter->hw_tcs; in ixgbe_alloc_q_vector()
845 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { in ixgbe_alloc_q_vector()
846 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_alloc_q_vector()
847 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_alloc_q_vector()
860 return -ENOMEM; in ixgbe_alloc_q_vector()
863 if (cpu != -1) in ixgbe_alloc_q_vector()
864 cpumask_set_cpu(cpu, &q_vector->affinity_mask); in ixgbe_alloc_q_vector()
865 q_vector->numa_node = node; in ixgbe_alloc_q_vector()
869 q_vector->cpu = -1; in ixgbe_alloc_q_vector()
873 netif_napi_add(adapter->netdev, &q_vector->napi, in ixgbe_alloc_q_vector()
877 adapter->q_vector[v_idx] = q_vector; in ixgbe_alloc_q_vector()
878 q_vector->adapter = adapter; in ixgbe_alloc_q_vector()
879 q_vector->v_idx = v_idx; in ixgbe_alloc_q_vector()
882 q_vector->tx.work_limit = adapter->tx_work_limit; in ixgbe_alloc_q_vector()
885 q_vector->tx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
887 q_vector->rx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
893 if (adapter->tx_itr_setting == 1) in ixgbe_alloc_q_vector()
894 q_vector->itr = IXGBE_12K_ITR; in ixgbe_alloc_q_vector()
896 q_vector->itr = adapter->tx_itr_setting; in ixgbe_alloc_q_vector()
899 if (adapter->rx_itr_setting == 1) in ixgbe_alloc_q_vector()
900 q_vector->itr = IXGBE_20K_ITR; in ixgbe_alloc_q_vector()
902 q_vector->itr = adapter->rx_itr_setting; in ixgbe_alloc_q_vector()
906 ring = q_vector->ring; in ixgbe_alloc_q_vector()
910 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
911 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
914 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
917 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
920 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
921 ring->queue_index = txr_idx; in ixgbe_alloc_q_vector()
924 WRITE_ONCE(adapter->tx_ring[txr_idx], ring); in ixgbe_alloc_q_vector()
927 txr_count--; in ixgbe_alloc_q_vector()
936 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
937 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
940 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
943 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
946 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
947 ring->queue_index = xdp_idx; in ixgbe_alloc_q_vector()
951 WRITE_ONCE(adapter->xdp_ring[xdp_idx], ring); in ixgbe_alloc_q_vector()
954 xdp_count--; in ixgbe_alloc_q_vector()
963 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
964 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
967 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
970 ixgbe_add_ring(ring, &q_vector->rx); in ixgbe_alloc_q_vector()
976 if (adapter->hw.mac.type == ixgbe_mac_82599EB) in ixgbe_alloc_q_vector()
977 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); in ixgbe_alloc_q_vector()
980 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { in ixgbe_alloc_q_vector()
982 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_alloc_q_vector()
983 if ((rxr_idx >= f->offset) && in ixgbe_alloc_q_vector()
984 (rxr_idx < f->offset + f->indices)) in ixgbe_alloc_q_vector()
985 set_bit(__IXGBE_RX_FCOE, &ring->state); in ixgbe_alloc_q_vector()
990 ring->count = adapter->rx_ring_count; in ixgbe_alloc_q_vector()
991 ring->queue_index = rxr_idx; in ixgbe_alloc_q_vector()
994 WRITE_ONCE(adapter->rx_ring[rxr_idx], ring); in ixgbe_alloc_q_vector()
997 rxr_count--; in ixgbe_alloc_q_vector()
1008 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
1009 * @adapter: board private structure to initialize
1018 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; in ixgbe_free_q_vector()
1021 ixgbe_for_each_ring(ring, q_vector->tx) { in ixgbe_free_q_vector()
1023 WRITE_ONCE(adapter->xdp_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1025 WRITE_ONCE(adapter->tx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1028 ixgbe_for_each_ring(ring, q_vector->rx) in ixgbe_free_q_vector()
1029 WRITE_ONCE(adapter->rx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1031 adapter->q_vector[v_idx] = NULL; in ixgbe_free_q_vector()
1032 __netif_napi_del(&q_vector->napi); in ixgbe_free_q_vector()
1043 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
1044 * @adapter: board private structure to initialize
1046 * We allocate one q_vector per queue interrupt. If allocation fails we
1047 * return -ENOMEM.
1051 int q_vectors = adapter->num_q_vectors; in ixgbe_alloc_q_vectors()
1052 int rxr_remaining = adapter->num_rx_queues; in ixgbe_alloc_q_vectors()
1053 int txr_remaining = adapter->num_tx_queues; in ixgbe_alloc_q_vectors()
1054 int xdp_remaining = adapter->num_xdp_queues; in ixgbe_alloc_q_vectors()
1058 /* only one q_vector if MSI-X is disabled. */ in ixgbe_alloc_q_vectors()
1059 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_alloc_q_vectors()
1071 rxr_remaining--; in ixgbe_alloc_q_vectors()
1077 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1078 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1079 int xqpv = DIV_ROUND_UP(xdp_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1090 rxr_remaining -= rqpv; in ixgbe_alloc_q_vectors()
1091 txr_remaining -= tqpv; in ixgbe_alloc_q_vectors()
1092 xdp_remaining -= xqpv; in ixgbe_alloc_q_vectors()
1098 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_alloc_q_vectors()
1099 if (adapter->rx_ring[i]) in ixgbe_alloc_q_vectors()
1100 adapter->rx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1103 for (i = 0; i < adapter->num_tx_queues; i++) { in ixgbe_alloc_q_vectors()
1104 if (adapter->tx_ring[i]) in ixgbe_alloc_q_vectors()
1105 adapter->tx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1108 for (i = 0; i < adapter->num_xdp_queues; i++) { in ixgbe_alloc_q_vectors()
1109 if (adapter->xdp_ring[i]) in ixgbe_alloc_q_vectors()
1110 adapter->xdp_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1116 adapter->num_tx_queues = 0; in ixgbe_alloc_q_vectors()
1117 adapter->num_xdp_queues = 0; in ixgbe_alloc_q_vectors()
1118 adapter->num_rx_queues = 0; in ixgbe_alloc_q_vectors()
1119 adapter->num_q_vectors = 0; in ixgbe_alloc_q_vectors()
1121 while (v_idx--) in ixgbe_alloc_q_vectors()
1124 return -ENOMEM; in ixgbe_alloc_q_vectors()
1128 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
1129 * @adapter: board private structure to initialize
1137 int v_idx = adapter->num_q_vectors; in ixgbe_free_q_vectors()
1139 adapter->num_tx_queues = 0; in ixgbe_free_q_vectors()
1140 adapter->num_xdp_queues = 0; in ixgbe_free_q_vectors()
1141 adapter->num_rx_queues = 0; in ixgbe_free_q_vectors()
1142 adapter->num_q_vectors = 0; in ixgbe_free_q_vectors()
1144 while (v_idx--) in ixgbe_free_q_vectors()
1150 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { in ixgbe_reset_interrupt_capability()
1151 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_reset_interrupt_capability()
1152 pci_disable_msix(adapter->pdev); in ixgbe_reset_interrupt_capability()
1153 kfree(adapter->msix_entries); in ixgbe_reset_interrupt_capability()
1154 adapter->msix_entries = NULL; in ixgbe_reset_interrupt_capability()
1155 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { in ixgbe_reset_interrupt_capability()
1156 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; in ixgbe_reset_interrupt_capability()
1157 pci_disable_msi(adapter->pdev); in ixgbe_reset_interrupt_capability()
1162 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1163 * @adapter: board private structure to initialize
1172 /* We will try to get MSI-X interrupts first */ in ixgbe_set_interrupt_capability()
1176 /* At this point, we do not have MSI-X capabilities. We need to in ixgbe_set_interrupt_capability()
1177 * reconfigure or disable various features which require MSI-X in ixgbe_set_interrupt_capability()
1182 if (adapter->hw_tcs > 1) { in ixgbe_set_interrupt_capability()
1184 netdev_reset_tc(adapter->netdev); in ixgbe_set_interrupt_capability()
1186 if (adapter->hw.mac.type == ixgbe_mac_82598EB) in ixgbe_set_interrupt_capability()
1187 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; in ixgbe_set_interrupt_capability()
1189 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; in ixgbe_set_interrupt_capability()
1190 adapter->temp_dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1191 adapter->dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1194 adapter->hw_tcs = 0; in ixgbe_set_interrupt_capability()
1195 adapter->dcb_cfg.num_tcs.pg_tcs = 1; in ixgbe_set_interrupt_capability()
1196 adapter->dcb_cfg.num_tcs.pfc_tcs = 1; in ixgbe_set_interrupt_capability()
1198 /* Disable SR-IOV support */ in ixgbe_set_interrupt_capability()
1199 e_dev_warn("Disabling SR-IOV support\n"); in ixgbe_set_interrupt_capability()
1204 adapter->ring_feature[RING_F_RSS].limit = 1; in ixgbe_set_interrupt_capability()
1210 adapter->num_q_vectors = 1; in ixgbe_set_interrupt_capability()
1212 err = pci_enable_msi(adapter->pdev); in ixgbe_set_interrupt_capability()
1217 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; in ixgbe_set_interrupt_capability()
1221 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
1222 * @adapter: board private structure to initialize
1225 * - Kernel support (MSI, MSI-X)
1226 * - which can be user-defined (via MODULE_PARAM)
1227 * - Hardware queue count (num_*_queues)
1228 * - defined by miscellaneous hardware support/features (RSS, etc.)
1249 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", in ixgbe_init_interrupt_scheme()
1250 adapter->num_rx_queues, adapter->num_tx_queues, in ixgbe_init_interrupt_scheme()
1251 adapter->num_xdp_queues); in ixgbe_init_interrupt_scheme()
1253 set_bit(__IXGBE_DOWN, &adapter->state); in ixgbe_init_interrupt_scheme()
1263 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
1264 * @adapter: board private structure to clear interrupt scheme on
1267 * to pre-load conditions
1271 adapter->num_tx_queues = 0; in ixgbe_clear_interrupt_scheme()
1272 adapter->num_xdp_queues = 0; in ixgbe_clear_interrupt_scheme()
1273 adapter->num_rx_queues = 0; in ixgbe_clear_interrupt_scheme()
1283 u16 i = tx_ring->next_to_use; in ixgbe_tx_ctxtdesc()
1288 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; in ixgbe_tx_ctxtdesc()
1293 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); in ixgbe_tx_ctxtdesc()
1294 context_desc->fceof_saidx = cpu_to_le32(fceof_saidx); in ixgbe_tx_ctxtdesc()
1295 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); in ixgbe_tx_ctxtdesc()
1296 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); in ixgbe_tx_ctxtdesc()