Lines Matching +full:flow +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
36 timeout--; in igc_disable_pcie_master()
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; in igc_disable_pcie_master()
50 * igc_init_rx_addrs - Initialize receive addresses
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs()
68 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igc_init_rx_addrs()
69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1); in igc_init_rx_addrs()
71 hw->mac.ops.rar_set(hw, mac_addr, i); in igc_init_rx_addrs()
75 * igc_set_fc_watermarks - Set flow control high/low watermarks
78 * Sets the flow control high/low threshold (watermark) registers. If
79 * flow control XON frame transmission is enabled, then set XON frame
86 /* Set the flow control receive threshold registers. Normally, in igc_set_fc_watermarks()
92 if (hw->fc.current_mode & igc_fc_tx_pause) { in igc_set_fc_watermarks()
97 fcrtl = hw->fc.low_water; in igc_set_fc_watermarks()
98 if (hw->fc.send_xon) in igc_set_fc_watermarks()
101 fcrth = hw->fc.high_water; in igc_set_fc_watermarks()
110 * igc_setup_link - Setup flow control and link settings
113 * Determines which flow control settings to use, then configures flow
114 * control. Calls the appropriate media-specific link configuration
129 /* If requested flow control is set to default, set flow control in igc_setup_link()
132 if (hw->fc.requested_mode == igc_fc_default) in igc_setup_link()
133 hw->fc.requested_mode = igc_fc_full; in igc_setup_link()
135 /* We want to save off the original Flow Control configuration just in igc_setup_link()
137 * hub or switch with different Flow Control capabilities. in igc_setup_link()
139 hw->fc.current_mode = hw->fc.requested_mode; in igc_setup_link()
141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in igc_setup_link()
144 ret_val = hw->mac.ops.setup_physical_interface(hw); in igc_setup_link()
148 /* Initialize the flow control address, type, and PAUSE timer in igc_setup_link()
149 * registers to their default values. This is done even if flow in igc_setup_link()
150 * control is disabled, because it does not hurt anything to in igc_setup_link()
153 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); in igc_setup_link()
158 wr32(IGC_FCTTV, hw->fc.pause_time); in igc_setup_link()
167 * igc_force_mac_fc - Force the MAC's flow control settings
170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
171 * device control register to reflect the adapter settings. TFCE and RFCE
183 /* Because we didn't get link via the internal auto-negotiation in igc_force_mac_fc()
185 * auto-neg), we have to manually enable/disable transmit an in igc_force_mac_fc()
186 * receive flow control. in igc_force_mac_fc()
188 * The "Case" statement below enables/disable flow control in igc_force_mac_fc()
189 * according to the "hw->fc.current_mode" parameter. in igc_force_mac_fc()
192 * 0: Flow control is completely disabled in igc_force_mac_fc()
193 * 1: Rx flow control is enabled (we can receive pause in igc_force_mac_fc()
195 * 2: Tx flow control is enabled (we can send pause frames in igc_force_mac_fc()
197 * 3: Both Rx and TX flow control (symmetric) is enabled. in igc_force_mac_fc()
200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); in igc_force_mac_fc()
202 switch (hw->fc.current_mode) { in igc_force_mac_fc()
218 hw_dbg("Flow control param set incorrectly\n"); in igc_force_mac_fc()
219 ret_val = -IGC_ERR_CONFIG; in igc_force_mac_fc()
230 * igc_clear_hw_cntrs_base - Clear base hardware counters
312 * igc_rar_set - Set receive address register
337 /* Some bridges will combine consecutive 32-bit writes into in igc_rar_set()
348 * igc_check_for_copper_link - Check for link (Copper)
357 struct igc_mac_info *mac = &hw->mac; in igc_check_for_copper_link()
361 /* We only want to go out to the PHY registers to see if Auto-Neg in igc_check_for_copper_link()
366 if (!mac->get_link_status) { in igc_check_for_copper_link()
382 mac->get_link_status = false; in igc_check_for_copper_link()
385 * immediately after link-up in igc_check_for_copper_link()
392 if (!mac->autoneg) { in igc_check_for_copper_link()
393 ret_val = -IGC_ERR_CONFIG; in igc_check_for_copper_link()
397 /* Auto-Neg is enabled. Auto Speed Detection takes care in igc_check_for_copper_link()
403 /* Configure Flow Control now that Auto-Neg has completed. in igc_check_for_copper_link()
404 * First, we need to restore the desired flow control in igc_check_for_copper_link()
405 * settings because we may have had to re-autoneg with a in igc_check_for_copper_link()
410 hw_dbg("Error configuring flow control\n"); in igc_check_for_copper_link()
422 * igc_config_collision_dist - Configure collision distance
443 * igc_config_fc_after_link_up - Configures flow control after link
446 * Checks the status of auto-negotiation after link up to ensure that the
448 * flow control needs to be forced also. If auto-negotiation is enabled
449 * and did not fail, then we configure flow control based on our link
455 struct igc_mac_info *mac = &hw->mac; in igc_config_fc_after_link_up()
459 /* Check for the case where we have fiber media and auto-neg failed in igc_config_fc_after_link_up()
463 if (mac->autoneg_failed) in igc_config_fc_after_link_up()
467 hw_dbg("Error forcing flow control settings\n"); in igc_config_fc_after_link_up()
471 /* Check for the case where we have copper media and auto-neg is in igc_config_fc_after_link_up()
472 * enabled. In this case, we need to check and see if Auto-Neg in igc_config_fc_after_link_up()
474 * flow control configured. in igc_config_fc_after_link_up()
476 if (mac->autoneg) { in igc_config_fc_after_link_up()
481 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igc_config_fc_after_link_up()
485 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igc_config_fc_after_link_up()
499 * flow control was negotiated. in igc_config_fc_after_link_up()
501 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, in igc_config_fc_after_link_up()
505 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, in igc_config_fc_after_link_up()
511 * Page Ability Register (Address 5) determine flow control in igc_config_fc_after_link_up()
514 * 1999, describes these PAUSE resolution bits and how flow in igc_config_fc_after_link_up()
515 * control is determined based upon these settings. in igc_config_fc_after_link_up()
520 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up()
531 * Symmetric Flow Control is enabled at both ends. The in igc_config_fc_after_link_up()
534 * For Symmetric Flow Control: in igc_config_fc_after_link_up()
538 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up()
546 * FULL flow control because we could not advertise RX in igc_config_fc_after_link_up()
550 if (hw->fc.requested_mode == igc_fc_full) { in igc_config_fc_after_link_up()
551 hw->fc.current_mode = igc_fc_full; in igc_config_fc_after_link_up()
552 hw_dbg("Flow Control = FULL.\n"); in igc_config_fc_after_link_up()
554 hw->fc.current_mode = igc_fc_rx_pause; in igc_config_fc_after_link_up()
555 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igc_config_fc_after_link_up()
563 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up()
570 hw->fc.current_mode = igc_fc_tx_pause; in igc_config_fc_after_link_up()
571 hw_dbg("Flow Control = TX PAUSE frames only.\n"); in igc_config_fc_after_link_up()
577 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up()
584 hw->fc.current_mode = igc_fc_rx_pause; in igc_config_fc_after_link_up()
585 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igc_config_fc_after_link_up()
587 /* Per the IEEE spec, at this point flow control should be in igc_config_fc_after_link_up()
590 * desired flow control, but can be forced on the link in igc_config_fc_after_link_up()
591 * partner. So if we advertised no flow control, that is in igc_config_fc_after_link_up()
593 * receive capability (Rx Pause Only or Full Flow Control) in igc_config_fc_after_link_up()
595 * ourselves to enable Rx Flow Control only. We can do in igc_config_fc_after_link_up()
597 * didn't want flow control enabled, and we enable Rx, no in igc_config_fc_after_link_up()
600 * flow control enabled, then by us enabling RX only, we in igc_config_fc_after_link_up()
607 else if ((hw->fc.requested_mode == igc_fc_none) || in igc_config_fc_after_link_up()
608 (hw->fc.requested_mode == igc_fc_tx_pause) || in igc_config_fc_after_link_up()
609 (hw->fc.strict_ieee)) { in igc_config_fc_after_link_up()
610 hw->fc.current_mode = igc_fc_none; in igc_config_fc_after_link_up()
611 hw_dbg("Flow Control = NONE.\n"); in igc_config_fc_after_link_up()
613 hw->fc.current_mode = igc_fc_rx_pause; in igc_config_fc_after_link_up()
614 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igc_config_fc_after_link_up()
617 /* Now we need to do one last check... If we auto- in igc_config_fc_after_link_up()
618 * negotiated to HALF DUPLEX, flow control should not be in igc_config_fc_after_link_up()
621 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); in igc_config_fc_after_link_up()
628 hw->fc.current_mode = igc_fc_none; in igc_config_fc_after_link_up()
631 * controller to use the correct flow control settings. in igc_config_fc_after_link_up()
635 hw_dbg("Error forcing flow control settings\n"); in igc_config_fc_after_link_up()
645 * igc_get_auto_rd_done - Check for auto read completion
664 ret_val = -IGC_ERR_RESET; in igc_get_auto_rd_done()
673 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
692 if (hw->mac.type == igc_i225 && in igc_get_speed_and_duplex_copper()
720 * igc_put_hw_semaphore - Release hardware semaphore
737 * igc_enable_mng_pass_thru - Enable processing of ARP's
749 if (!hw->mac.asf_firmware_present) in igc_enable_mng_pass_thru()
757 if (hw->mac.arc_subsystem_valid) { in igc_enable_mng_pass_thru()
780 * igc_hash_mc_addr - Generate a multicast hash value
794 hash_mask = (hw->mac.mta_reg_count * 32) - 1; in igc_hash_mc_addr()
796 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts in igc_hash_mc_addr()
806 * left-shifts where the MSB of mc_addr[5] would still fall within in igc_hash_mc_addr()
809 * remaining number of bits. Thus 8 - bit_shift. The rest of the in igc_hash_mc_addr()
812 * 8-bit shifting total. in igc_hash_mc_addr()
815 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask), in igc_hash_mc_addr()
827 switch (hw->mac.mc_filter_type) { in igc_hash_mc_addr()
842 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | in igc_hash_mc_addr()
849 * igc_update_mc_addr_list - Update Multicast addresses
864 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in igc_update_mc_addr_list()
870 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igc_update_mc_addr_list()
873 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); in igc_update_mc_addr_list()
878 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) in igc_update_mc_addr_list()
879 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]); in igc_update_mc_addr_list()