Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
19 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
20 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
21 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
22 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
96 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
97 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
215 #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
216 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
217 #define IGC_ICR_RXO BIT(6) /* Rx overrun */
218 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
225 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
236 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
240 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
241 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
244 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
249 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
274 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
277 /* IPSec Encrypt Enable */
282 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
286 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
293 /* Enable XON frame transmission */
302 #define IGC_RCTL_EN 0x00000002 /* enable */
304 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
305 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
306 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
310 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
311 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
341 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
344 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
351 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
356 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
374 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
380 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
382 #define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */
401 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
417 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
420 /* GPY211 - I225 defines */
433 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
434 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
438 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
445 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
465 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
466 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
483 #define IGC_N0_QUEUE -1
505 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
506 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
511 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
512 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
514 /* Minimum time for 100BASE-T where no data will be transmit following move out
519 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */