Lines Matching +full:rx +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
58 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
62 /* Receive Descriptor - Advanced */
95 /* Transmit Descriptor - Advanced */
117 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
118 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
134 /* IPSec Encrypt Enable for ESP */
141 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
145 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
151 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
152 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
153 #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
154 #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
155 #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
158 #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
165 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
167 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
192 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31)  /* global VF LB enable */
206 #define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
212 #define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
213 #define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
215 #define E1000_DVMOLR_HIDEVLAN  0x20000000 /* Hide vlan enable */
216 #define E1000_DVMOLR_STRVLAN   0x40000000 /* Vlan stripping enable */
217 #define E1000_DVMOLR_STRCRC    0x80000000 /* CRC stripping enable */
245 /* RX packet buffer size defines */