Lines Matching full:rx
42 #define E1000_RCTL 0x00100 /* Rx Control - RW */
45 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
63 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
67 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
68 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
69 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
70 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
71 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
72 /* Split and Replication Rx Control - RW */
73 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
74 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
136 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
138 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
140 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
141 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
142 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
143 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
144 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
145 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
146 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
147 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
148 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
149 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
151 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
152 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
155 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
156 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
157 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
158 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
159 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
160 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
163 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
164 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
167 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
180 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
181 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
186 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
194 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
225 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
227 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
228 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
238 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
239 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */