Lines Matching +full:mac +full:- +full:only
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
143 return readw(hw->flash_address + reg); in __er16flash()
148 return readl(hw->flash_address + reg); in __er32flash()
153 writew(val, hw->flash_address + reg); in __ew16flash()
158 writel(val, hw->flash_address + reg); in __ew32flash()
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
199 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
200 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
203 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
211 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
212 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
216 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
222 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
223 /* Only unforce SMBus if ME is not active */ in e1000_phy_is_accessible_pchlan()
230 /* Unforce SMBus mode in MAC */ in e1000_phy_is_accessible_pchlan()
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
268 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); in e1000_toggle_lanphypc_pch_lpt()
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
290 struct e1000_adapter *adapter = hw->adapter; in e1000_init_phy_workarounds_pchlan()
295 * non-managed 82579 and newer adapters. in e1000_init_phy_workarounds_pchlan()
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
307 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is in e1000_init_phy_workarounds_pchlan()
317 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
328 * forcing MAC to SMBus mode first. in e1000_init_phy_workarounds_pchlan()
334 /* Wait 50 milliseconds for MAC to finish any retries in e1000_init_phy_workarounds_pchlan()
347 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
351 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
353 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
359 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
364 * so ensure that the MAC is also out of SMBus mode in e1000_init_phy_workarounds_pchlan()
373 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
380 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
384 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
404 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
410 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_init_phy_workarounds_pchlan()
411 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
424 * Initialize family-specific PHY parameters and function pointers.
428 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
431 phy->addr = 1; in e1000_init_phy_params_pchlan()
432 phy->reset_delay_us = 100; in e1000_init_phy_params_pchlan()
434 phy->ops.set_page = e1000_set_page_igp; in e1000_init_phy_params_pchlan()
435 phy->ops.read_reg = e1000_read_phy_reg_hv; in e1000_init_phy_params_pchlan()
436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
440 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
443 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_pchlan()
444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_pchlan()
445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_pchlan()
447 phy->id = e1000_phy_unknown; in e1000_init_phy_params_pchlan()
453 if (phy->id == e1000_phy_unknown) in e1000_init_phy_params_pchlan()
454 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) in e1000_init_phy_params_pchlan()
480 phy->type = e1000e_get_phy_type_from_id(phy->id); in e1000_init_phy_params_pchlan()
482 switch (phy->type) { in e1000_init_phy_params_pchlan()
486 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_pchlan()
487 phy->ops.force_speed_duplex = in e1000_init_phy_params_pchlan()
489 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_pchlan()
490 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_pchlan()
491 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_pchlan()
494 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_pchlan()
495 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_pchlan()
496 phy->ops.get_cable_length = e1000e_get_cable_length_m88; in e1000_init_phy_params_pchlan()
497 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_pchlan()
500 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_pchlan()
508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
511 * Initialize family-specific PHY parameters and function pointers.
515 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
519 phy->addr = 1; in e1000_init_phy_params_ich8lan()
520 phy->reset_delay_us = 100; in e1000_init_phy_params_ich8lan()
522 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_ich8lan()
523 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_ich8lan()
525 /* We may need to do this twice - once for IGP and if that fails, in e1000_init_phy_params_ich8lan()
530 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
531 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
539 phy->id = 0; in e1000_init_phy_params_ich8lan()
540 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && in e1000_init_phy_params_ich8lan()
549 switch (phy->id) { in e1000_init_phy_params_ich8lan()
551 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_ich8lan()
552 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
553 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
554 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
555 phy->ops.get_info = e1000e_get_phy_info_igp; in e1000_init_phy_params_ich8lan()
556 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_ich8lan()
557 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; in e1000_init_phy_params_ich8lan()
562 phy->type = e1000_phy_ife; in e1000_init_phy_params_ich8lan()
563 phy->autoneg_mask = E1000_ALL_NOT_GIG; in e1000_init_phy_params_ich8lan()
564 phy->ops.get_info = e1000_get_phy_info_ife; in e1000_init_phy_params_ich8lan()
565 phy->ops.check_polarity = e1000_check_polarity_ife; in e1000_init_phy_params_ich8lan()
566 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; in e1000_init_phy_params_ich8lan()
569 phy->type = e1000_phy_bm; in e1000_init_phy_params_ich8lan()
570 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
571 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
572 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
573 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_ich8lan()
574 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_ich8lan()
575 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_ich8lan()
576 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_ich8lan()
579 return -E1000_ERR_PHY; in e1000_init_phy_params_ich8lan()
586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
589 * Initialize family-specific NVM parameters and function
594 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
600 nvm->type = e1000_nvm_flash_sw; in e1000_init_nvm_params_ich8lan()
602 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
609 nvm->flash_base_addr = 0; in e1000_init_nvm_params_ich8lan()
612 nvm->flash_bank_size = nvm_size / 2; in e1000_init_nvm_params_ich8lan()
614 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
616 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
619 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
621 return -E1000_ERR_CONFIG; in e1000_init_nvm_params_ich8lan()
626 /* sector_X_addr is a "sector"-aligned address (4096 bytes) in e1000_init_nvm_params_ich8lan()
633 /* flash_base_addr is byte-aligned */ in e1000_init_nvm_params_ich8lan()
634 nvm->flash_base_addr = sector_base_addr in e1000_init_nvm_params_ich8lan()
640 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) in e1000_init_nvm_params_ich8lan()
642 nvm->flash_bank_size /= 2; in e1000_init_nvm_params_ich8lan()
644 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
647 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; in e1000_init_nvm_params_ich8lan()
650 for (i = 0; i < nvm->word_size; i++) { in e1000_init_nvm_params_ich8lan()
651 dev_spec->shadow_ram[i].modified = false; in e1000_init_nvm_params_ich8lan()
652 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_init_nvm_params_ich8lan()
659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
662 * Initialize family-specific MAC parameters and function
667 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan() local
670 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
673 mac->mta_reg_count = 32; in e1000_init_mac_params_ich8lan()
675 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
676 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
677 mac->rar_entry_count--; in e1000_init_mac_params_ich8lan()
679 mac->has_fwsm = true; in e1000_init_mac_params_ich8lan()
681 mac->arc_subsystem_valid = false; in e1000_init_mac_params_ich8lan()
683 mac->adaptive_ifs = true; in e1000_init_mac_params_ich8lan()
686 switch (mac->type) { in e1000_init_mac_params_ich8lan()
691 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; in e1000_init_mac_params_ich8lan()
693 mac->ops.id_led_init = e1000e_id_led_init_generic; in e1000_init_mac_params_ich8lan()
695 mac->ops.blink_led = e1000e_blink_led_generic; in e1000_init_mac_params_ich8lan()
697 mac->ops.setup_led = e1000e_setup_led_generic; in e1000_init_mac_params_ich8lan()
699 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; in e1000_init_mac_params_ich8lan()
701 mac->ops.led_on = e1000_led_on_ich8lan; in e1000_init_mac_params_ich8lan()
702 mac->ops.led_off = e1000_led_off_ich8lan; in e1000_init_mac_params_ich8lan()
705 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
706 mac->ops.rar_set = e1000_rar_set_pch2lan; in e1000_init_mac_params_ich8lan()
716 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; in e1000_init_mac_params_ich8lan()
718 mac->ops.id_led_init = e1000_id_led_init_pchlan; in e1000_init_mac_params_ich8lan()
720 mac->ops.setup_led = e1000_setup_led_pchlan; in e1000_init_mac_params_ich8lan()
722 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; in e1000_init_mac_params_ich8lan()
724 mac->ops.led_on = e1000_led_on_pchlan; in e1000_init_mac_params_ich8lan()
725 mac->ops.led_off = e1000_led_off_pchlan; in e1000_init_mac_params_ich8lan()
731 if (mac->type >= e1000_pch_lpt) { in e1000_init_mac_params_ich8lan()
732 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
733 mac->ops.rar_set = e1000_rar_set_pch_lpt; in e1000_init_mac_params_ich8lan()
734 mac->ops.setup_physical_interface = in e1000_init_mac_params_ich8lan()
736 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; in e1000_init_mac_params_ich8lan()
739 /* Enable PCS Lock-loss workaround for ICH8 */ in e1000_init_mac_params_ich8lan()
740 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
747 * __e1000_access_emi_reg_locked - Read/write EMI register
773 * e1000_read_emi_reg_locked - Read Extended Management Interface register
786 * e1000_write_emi_reg_locked - Write Extended Management Interface register
799 * e1000_set_eee_pchlan - Enable/disable EEE support
804 * register bits will remain set only if/when link is up.
814 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
818 switch (hw->phy.type) { in e1000_set_eee_pchlan()
833 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
845 if (!dev_spec->eee_disable) { in e1000_set_eee_pchlan()
848 &dev_spec->eee_lp_ability); in e1000_set_eee_pchlan()
857 /* Enable EEE only for speeds in which the link partner is in e1000_set_eee_pchlan()
860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) in e1000_set_eee_pchlan()
863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { in e1000_set_eee_pchlan()
869 * partner's EEE in 100 ability if full-duplex in e1000_set_eee_pchlan()
872 dev_spec->eee_lp_ability &= in e1000_set_eee_pchlan()
877 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ in e1000_set_eee_pchlan()
895 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
907 * the de-assertion of the clock request when in 1Gpbs mode.
908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
919 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
946 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
951 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
990 * e1000_platform_pm_pch_lpt - Set platform power management values
994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1018 if (!hw->adapter->max_frame_size) { in e1000_platform_pm_pch_lpt()
1020 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1023 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1026 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1035 * a 3-bit encoded scale (only 0-5 are valid) multiplied by in e1000_platform_pm_pch_lpt()
1036 * a 10-bit value (0-1023) to provide a range from 1 ns to in e1000_platform_pm_pch_lpt()
1037 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, in e1000_platform_pm_pch_lpt()
1041 value = (rxa > hw->adapter->max_frame_size) ? in e1000_platform_pm_pch_lpt()
1042 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : in e1000_platform_pm_pch_lpt()
1051 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1056 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, in e1000_platform_pm_pch_lpt()
1058 pci_read_config_word(hw->adapter->pdev, in e1000_platform_pm_pch_lpt()
1066 /* Set Snoop and No-Snoop latencies the same */ in e1000_platform_pm_pch_lpt()
1074 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1090 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1091 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1092 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1093 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1094 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1095 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1112 /* Bail if link is re-acquired */ in e1000_enable_ulp_lpt_lp()
1114 return -E1000_ERR_PHY; in e1000_enable_ulp_lpt_lp()
1126 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1137 /* Force SMBus mode in MAC */ in e1000_enable_ulp_lpt_lp()
1145 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1184 /* Set Disable SMBus Release on PERST# in MAC */ in e1000_enable_ulp_lpt_lp()
1193 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1202 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1207 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1213 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1217 * Un-configure ULP mode when link is up, the system is transitioned from
1219 * system, poll for an indication from ME that ULP has been un-configured.
1220 * If not on an ME enabled system, un-configure the ULP mode by software.
1224 * the driver or during Sx->S0 transitions, this is called with force=true
1234 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1236 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1237 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1238 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1239 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1244 /* Request ME un-configure ULP mode in the PHY */ in e1000_disable_ulp_lpt_lp()
1254 ret_val = -E1000_ERR_PHY; in e1000_disable_ulp_lpt_lp()
1276 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1287 /* The MAC might be in PCIe mode, so temporarily force to in e1000_disable_ulp_lpt_lp()
1304 /* Unforce SMBus mode in MAC */ in e1000_disable_ulp_lpt_lp()
1310 * hardware. Re-Enable K1 in the PHY when exiting ULP. in e1000_disable_ulp_lpt_lp()
1336 /* Clear Disable SMBus Release on PERST# in MAC */ in e1000_disable_ulp_lpt_lp()
1342 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1351 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1357 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1366 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan() local
1372 /* We only want to go out to the PHY registers to see if Auto-Neg in e1000_check_for_copper_link_ich8lan()
1377 if (!mac->get_link_status) in e1000_check_for_copper_link_ich8lan()
1379 mac->get_link_status = false; in e1000_check_for_copper_link_ich8lan()
1389 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1395 /* When connected at 10Mbps half-duplex, some parts are excessively in e1000_check_for_copper_link_ich8lan()
1399 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1410 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1423 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1427 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1433 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1445 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1450 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1454 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1459 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1464 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1472 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1485 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1489 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1496 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1509 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1518 /* Work-around I218 hang issue */ in e1000_check_for_copper_link_ich8lan()
1519 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1520 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1521 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1522 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1527 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1537 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1539 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1542 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1543 /* FEXTNVM6 K1-off workaround - for SPT only */ in e1000_check_for_copper_link_ich8lan()
1558 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1565 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1571 /* Workaround for PCHx parts in half-duplex: in e1000_check_for_copper_link_ich8lan()
1573 * when it is passed from the PHY to the MAC to prevent in e1000_check_for_copper_link_ich8lan()
1574 * the MAC from misinterpreting the packet type. in e1000_check_for_copper_link_ich8lan()
1589 * immediately after link-up in e1000_check_for_copper_link_ich8lan()
1594 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1603 if (!mac->autoneg) in e1000_check_for_copper_link_ich8lan()
1604 return -E1000_ERR_CONFIG; in e1000_check_for_copper_link_ich8lan()
1606 /* Auto-Neg is enabled. Auto Speed Detection takes care in e1000_check_for_copper_link_ich8lan()
1607 * of MAC speed/duplex configuration. So we only need to in e1000_check_for_copper_link_ich8lan()
1608 * configure Collision Distance in the MAC. in e1000_check_for_copper_link_ich8lan()
1610 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1612 /* Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_copper_link_ich8lan()
1614 * settings because we may have had to re-autoneg with a in e1000_check_for_copper_link_ich8lan()
1624 mac->get_link_status = true; in e1000_check_for_copper_link_ich8lan()
1630 struct e1000_hw *hw = &adapter->hw; in e1000_get_variants_ich8lan()
1641 switch (hw->mac.type) { in e1000_get_variants_ich8lan()
1666 if ((adapter->hw.phy.type == e1000_phy_ife) || in e1000_get_variants_ich8lan()
1667 ((adapter->hw.mac.type >= e1000_pch2lan) && in e1000_get_variants_ich8lan()
1669 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; in e1000_get_variants_ich8lan()
1670 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; in e1000_get_variants_ich8lan()
1672 hw->mac.ops.blink_led = NULL; in e1000_get_variants_ich8lan()
1675 if ((adapter->hw.mac.type == e1000_ich8lan) && in e1000_get_variants_ich8lan()
1676 (adapter->hw.phy.type != e1000_phy_ife)) in e1000_get_variants_ich8lan()
1677 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; in e1000_get_variants_ich8lan()
1680 if ((adapter->hw.mac.type == e1000_pch2lan) && in e1000_get_variants_ich8lan()
1682 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; in e1000_get_variants_ich8lan()
1690 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1703 * e1000_release_nvm_ich8lan - Release NVM mutex
1714 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1718 * MAC CSR accesses.
1726 &hw->adapter->state)) { in e1000_acquire_swflag_ich8lan()
1728 return -E1000_ERR_PHY; in e1000_acquire_swflag_ich8lan()
1737 timeout--; in e1000_acquire_swflag_ich8lan()
1742 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1757 timeout--; in e1000_acquire_swflag_ich8lan()
1765 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1771 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_acquire_swflag_ich8lan()
1777 * e1000_release_swflag_ich8lan - Release software control flag
1781 * MAC CSR accesses.
1796 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_release_swflag_ich8lan()
1800 * e1000_check_mng_mode_ich8lan - Checks management mode
1804 * This is a function pointer entry point only called by read/write
1818 * e1000_check_mng_mode_pchlan - Checks management mode
1822 * This is a function pointer entry point only called by read/write
1835 * e1000_rar_set_pch2lan - Set receive address register
1842 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1843 * Use SHRA[0-3] in place of those reserved for ME.
1858 /* If MAC address zero, no need to set the AV bit */ in e1000_rar_set_pch2lan()
1870 /* RAR[1-6] are owned by manageability. Skip those and program the in e1000_rar_set_pch2lan()
1873 if (index < (u32)(hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
1880 ew32(SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
1882 ew32(SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
1888 if ((er32(SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
1889 (er32(SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
1892 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", in e1000_rar_set_pch2lan()
1893 (index - 1), er32(FWSM)); in e1000_rar_set_pch2lan()
1898 return -E1000_ERR_CONFIG; in e1000_rar_set_pch2lan()
1902 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1906 * program. SHRA[0-10] are the shared receive address registers
1922 num_entries = hw->mac.rar_entry_count; in e1000_rar_get_count_pch_lpt()
1925 /* Only RAR[0] available */ in e1000_rar_get_count_pch_lpt()
1929 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ in e1000_rar_get_count_pch_lpt()
1938 * e1000_rar_set_pch_lpt - Set receive address registers
1945 * contain the MAC address. SHRA[0-10] are the shared receive address
1961 /* If MAC address zero, no need to set the AV bit */ in e1000_rar_set_pch_lpt()
1974 * it is using - those registers are unavailable for use. in e1000_rar_set_pch_lpt()
1976 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
1992 ew32(SHRAL_PCH_LPT(index - 1), rar_low); in e1000_rar_set_pch_lpt()
1994 ew32(SHRAH_PCH_LPT(index - 1), rar_high); in e1000_rar_set_pch_lpt()
2000 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2001 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2008 return -E1000_ERR_CONFIG; in e1000_rar_set_pch_lpt()
2012 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2016 * This is a function pointer entry point only called by
2031 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2055 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2057 if (freq--) { in e1000_write_smbus_addr()
2062 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); in e1000_write_smbus_addr()
2072 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2080 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2091 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2093 if (phy->type != e1000_phy_igp_3) in e1000_sw_lcd_config_ich8lan()
2096 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2097 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2116 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2128 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2141 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2143 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2190 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2195 * e1000_k1_gig_workaround_hv - K1 Si workaround
2199 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2208 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2210 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2214 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2220 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2236 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2266 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2272 * e1000_configure_k1_ich8lan - Configure K1 power state
2279 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2324 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2338 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2341 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2345 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2379 /* Set Restart auto-neg to activate the bits */ in e1000_oem_bits_config_ich8lan()
2380 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2381 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2387 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2393 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2413 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2423 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2427 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2433 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2434 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2435 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2447 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2451 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2460 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2464 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2466 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2478 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2491 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2497 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2506 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2514 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2516 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2518 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2522 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2524 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2532 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2536 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2548 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2559 * SHRAL/H) and initial CRC values to the MAC in e1000_lv_jumbo_workaround_ich8lan()
2561 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2582 /* Enable jumbo frame workaround in the MAC */ in e1000_lv_jumbo_workaround_ich8lan()
2641 /* Write MAC register values back to h/w defaults */ in e1000_lv_jumbo_workaround_ich8lan()
2699 /* re-enable Rx path after enabling/disabling workaround */ in e1000_lv_jumbo_workaround_ich8lan()
2704 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2713 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2721 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2731 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2737 * e1000_k1_gig_workaround_lv - K1 Si workaround
2748 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
2784 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2795 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
2809 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2812 * Check the appropriate indication the MAC has finished configuring the
2824 } while ((!data) && --loop); in e1000_lan_init_done_ich8lan()
2840 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2848 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
2854 /* Perform any necessary post-reset workarounds */ in e1000_post_phy_reset_ich8lan()
2855 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
2871 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
2885 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
2886 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_post_phy_reset_ich8lan()
2893 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
2899 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
2906 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2917 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ in e1000_phy_hw_reset_ich8lan()
2918 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
2930 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2935 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2937 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2954 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
2961 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2970 * This is a function pointer entry point only called by
2975 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
2980 if (phy->type == e1000_phy_ife) in e1000_set_d0_lplu_state_ich8lan()
2989 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
2995 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3010 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3018 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_ich8lan()
3029 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_ich8lan()
3047 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3056 * This is a function pointer entry point only called by
3061 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3072 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3080 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state_ich8lan()
3091 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state_ich8lan()
3103 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_ich8lan()
3104 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_ich8lan()
3105 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_ich8lan()
3109 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3115 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3131 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3141 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3142 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); in e1000_valid_nvm_bank_detect_ich8lan()
3148 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3154 bank1_offset = nvm->flash_bank_size; in e1000_valid_nvm_bank_detect_ich8lan()
3186 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3199 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); in e1000_valid_nvm_bank_detect_ich8lan()
3229 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3234 * e1000_read_nvm_spt - NVM access for SPT
3245 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3246 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3254 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_spt()
3257 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_spt()
3261 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3269 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_spt()
3275 if (words - i == 1) { in e1000_read_nvm_spt()
3276 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_spt()
3278 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3280 offset_to_read = act_offset + i - in e1000_read_nvm_spt()
3295 if (!(dev_spec->shadow_ram[offset + i].modified) || in e1000_read_nvm_spt()
3296 !(dev_spec->shadow_ram[offset + i + 1].modified)) { in e1000_read_nvm_spt()
3304 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3306 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3309 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3311 dev_spec->shadow_ram[offset + i + 1].value; in e1000_read_nvm_spt()
3317 nvm->ops.release(hw); in e1000_read_nvm_spt()
3327 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3338 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3339 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3345 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_ich8lan()
3348 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_ich8lan()
3352 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3360 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_ich8lan()
3365 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_ich8lan()
3366 data[i] = dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_ich8lan()
3377 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3387 * e1000_flash_cycle_init_ich8lan - Initialize flash
3396 s32 ret_val = -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3403 return -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3409 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3428 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3452 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3466 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3479 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3485 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3501 return -E1000_ERR_NVM; in e1000_flash_cycle_ich8lan()
3505 * e1000_read_flash_dword_ich8lan - Read dword from flash
3522 * e1000_read_flash_word_ich8lan - Read word from flash
3540 * e1000_read_flash_byte_ich8lan - Read byte from flash
3553 /* In SPT, only 32 bits access is supported, in e1000_read_flash_byte_ich8lan()
3556 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3557 return -E1000_ERR_NVM; in e1000_read_flash_byte_ich8lan()
3570 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3585 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3589 return -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3592 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3603 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_read_flash_data_ich8lan()
3636 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data_ich8lan()
3646 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3660 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3663 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3664 return -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3666 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3675 * Therefore, only 32 bit access is supported in e1000_read_flash_data32_ich8lan()
3680 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_read_flash_data32_ich8lan()
3683 * Therefore, only 32 bit access is supported in e1000_read_flash_data32_ich8lan()
3711 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data32_ich8lan()
3721 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3732 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
3733 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
3736 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_write_nvm_ich8lan()
3739 return -E1000_ERR_NVM; in e1000_write_nvm_ich8lan()
3742 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
3745 dev_spec->shadow_ram[offset + i].modified = true; in e1000_write_nvm_ich8lan()
3746 dev_spec->shadow_ram[offset + i].value = data[i]; in e1000_write_nvm_ich8lan()
3749 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
3755 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3761 * checking for the modified bit and writing only the pending changes.
3767 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
3768 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
3777 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_spt()
3780 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
3793 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3799 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3814 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_spt()
3816 dword |= (dev_spec->shadow_ram[i].value & 0xffff); in e1000_update_nvm_checksum_spt()
3818 if (dev_spec->shadow_ram[i + 1].modified) { in e1000_update_nvm_checksum_spt()
3820 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) in e1000_update_nvm_checksum_spt()
3833 if (i == E1000_ICH_NVM_SIG_WORD - 1) in e1000_update_nvm_checksum_spt()
3853 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_spt()
3866 --act_offset; in e1000_update_nvm_checksum_spt()
3886 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; in e1000_update_nvm_checksum_spt()
3900 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_spt()
3901 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_spt()
3905 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
3911 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
3923 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3929 * checking for the modified bit and writing only the pending changes.
3935 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
3936 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
3945 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_ich8lan()
3948 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
3961 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
3967 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
3974 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_ich8lan()
3975 data = dev_spec->shadow_ram[i].value; in e1000_update_nvm_checksum_ich8lan()
4017 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_ich8lan()
4051 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_ich8lan()
4052 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_ich8lan()
4056 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4062 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4074 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4093 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4127 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4130 * To prevent malicious write/erase of the NVM, set it to be read-only
4132 * the flash control registers. The shadow-ram copy of the NVM will
4138 struct e1000_nvm_info *nvm = &hw->nvm; in e1000e_write_protect_nvm_ich8lan()
4143 nvm->ops.acquire(hw); in e1000e_write_protect_nvm_ich8lan()
4147 /* Write-protect GbE Sector of NVM */ in e1000e_write_protect_nvm_ich8lan()
4155 * PR0 to prevent the write-protection from being lifted. in e1000e_write_protect_nvm_ich8lan()
4163 nvm->ops.release(hw); in e1000e_write_protect_nvm_ich8lan()
4167 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4185 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4187 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4190 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4194 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4203 * flash. Therefore, only 32 bit access is supported in e1000_write_flash_data_ich8lan()
4205 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4211 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_write_flash_data_ich8lan()
4214 * not flash. Therefore, only 32 bit access is in e1000_write_flash_data_ich8lan()
4217 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4250 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data_ich8lan()
4259 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4275 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4277 return -E1000_ERR_NVM; in e1000_write_flash_data32_ich8lan()
4280 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4289 * flash. Therefore, only 32 bit access is supported in e1000_write_flash_data32_ich8lan()
4291 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4297 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_write_flash_data32_ich8lan()
4301 * not flash. Therefore, only 32 bit access is in e1000_write_flash_data32_ich8lan()
4304 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4334 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data32_ich8lan()
4343 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4359 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4387 return -E1000_ERR_NVM; in e1000_retry_write_flash_dword_ich8lan()
4393 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4419 return -E1000_ERR_NVM; in e1000_retry_write_flash_byte_ich8lan()
4425 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4434 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4438 /* bank size is in 16bit words - adjust to bytes */ in e1000_erase_flash_bank_ich8lan()
4439 u32 flash_bank_size = nvm->flash_bank_size * 2; in e1000_erase_flash_bank_ich8lan()
4455 * (ich9 only, otherwise error condition) in e1000_erase_flash_bank_ich8lan()
4477 return -E1000_ERR_NVM; in e1000_erase_flash_bank_ich8lan()
4481 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4496 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4503 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4537 * e1000_valid_led_default_ich8lan - Set the default LED settings
4562 * e1000_id_led_init_pchlan - store LED configurations
4576 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan() local
4583 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4587 mac->ledctl_default = er32(LEDCTL); in e1000_id_led_init_pchlan()
4588 mac->ledctl_mode1 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4589 mac->ledctl_mode2 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4598 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4599 mac->ledctl_mode1 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4604 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4605 mac->ledctl_mode1 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4615 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4616 mac->ledctl_mode2 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4621 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4622 mac->ledctl_mode2 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4634 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4642 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4647 /* ICH devices are "PCI Express"-ish. They have in e1000_get_bus_info_ich8lan()
4652 if (bus->width == e1000_bus_width_unknown) in e1000_get_bus_info_ich8lan()
4653 bus->width = e1000_bus_width_pcie_x1; in e1000_get_bus_info_ich8lan()
4659 * e1000_reset_hw_ich8lan - Reset the hardware
4663 * MAC.
4667 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4672 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_ich8lan()
4673 * on the last TLP read/write transaction when MAC is reset. in e1000_reset_hw_ich8lan()
4677 e_dbg("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_ich8lan()
4683 * any pending transactions to complete before we hit the MAC in e1000_reset_hw_ich8lan()
4693 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
4700 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
4707 dev_spec->nvm_k1_enabled = true; in e1000_reset_hw_ich8lan()
4709 dev_spec->nvm_k1_enabled = false; in e1000_reset_hw_ich8lan()
4714 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
4715 /* Full-chip reset requires MAC and PHY reset at the same in e1000_reset_hw_ich8lan()
4716 * time to make sure the interface between MAC and the in e1000_reset_hw_ich8lan()
4722 * non-managed 82579 in e1000_reset_hw_ich8lan()
4724 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
4735 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
4743 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_reset_hw_ich8lan()
4746 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
4759 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
4773 * e1000_init_hw_ich8lan - Initialize the hardware
4777 * - initialize hardware bits
4778 * - initialize LED identification
4779 * - setup receive address registers
4780 * - setup flow control
4781 * - setup transmit descriptors
4782 * - clear statistics
4786 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan() local
4794 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
4800 e1000e_init_rx_addrs(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
4804 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_ich8lan()
4811 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
4821 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
4823 /* Set the transmit descriptor write-back policy for both queues */ in e1000_init_hw_ich8lan()
4840 if (mac->type == e1000_ich8lan) in e1000_init_hw_ich8lan()
4861 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4874 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ in e1000_initialize_hw_bits_ich8lan()
4875 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
4891 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
4906 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
4912 /* work-around descriptor data corruption issue during nfs v2 udp in e1000_initialize_hw_bits_ich8lan()
4921 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
4926 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
4938 * e1000_setup_link_ich8lan - Setup flow control and link settings
4942 * control. Calls the appropriate media-specific link configuration
4951 if (hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_ich8lan()
4958 if (hw->fc.requested_mode == e1000_fc_default) { in e1000_setup_link_ich8lan()
4960 if (hw->mac.type == e1000_pchlan) in e1000_setup_link_ich8lan()
4961 hw->fc.requested_mode = e1000_fc_rx_pause; in e1000_setup_link_ich8lan()
4963 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
4969 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
4971 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in e1000_setup_link_ich8lan()
4974 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
4978 ew32(FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
4979 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
4980 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
4981 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
4982 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
4983 ew32(FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
4986 hw->fc.pause_time); in e1000_setup_link_ich8lan()
4995 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5013 /* Set the mac to wait the maximum time between each iteration in e1000_setup_copper_link_ich8lan()
5030 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5055 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5079 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5104 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5122 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5123 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { in e1000_get_link_up_info_ich8lan()
5131 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5134 * Work-around for 82566 Kumeran PCS lock loss:
5136 * speed is gigabit-
5143 * Note: this is only called for IGP3 copper when speed is 1gb.
5147 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5153 if (!dev_spec->kmrn_lock_loss_workaround_enabled) in e1000_kmrn_lock_loss_workaround_ich8lan()
5194 return -E1000_ERR_PHY; in e1000_kmrn_lock_loss_workaround_ich8lan()
5198 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5202 * If ICH8, set the current Kumeran workaround state (enabled - true
5203 * /disabled - false).
5208 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5210 if (hw->mac.type != e1000_ich8lan) { in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5211 e_dbg("Workaround applies to ICH8 only.\n"); in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5215 dev_spec->kmrn_lock_loss_workaround_enabled = state; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5219 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5222 * Workaround for 82566 power-down on D3 entry:
5224 * 2) write VR power-down enable
5234 if (hw->phy.type != e1000_phy_igp_3) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5248 if (hw->mac.type == e1000_ich8lan) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5251 /* Write VR power-down enable */ in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5270 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5275 * 1) Set Kumeran Near-end loopback
5276 * 2) Clear Kumeran Near-end loopback
5277 * Should only be called for ICH8[m] devices with any 1G Phy.
5284 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) in e1000e_gig_downshift_workaround_ich8lan()
5301 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5323 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5324 u16 phy_reg, device_id = hw->adapter->pdev->device; in e1000_suspend_workarounds_ich8lan()
5330 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5336 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5340 if (!dev_spec->eee_disable) { in e1000_suspend_workarounds_ich8lan()
5356 (dev_spec->eee_lp_ability & in e1000_suspend_workarounds_ich8lan()
5358 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5373 * is present, the driver must configure proxy to reset only on in e1000_suspend_workarounds_ich8lan()
5374 * power good. LPI (Low Power Idle) state must also reset only in e1000_suspend_workarounds_ich8lan()
5379 /* Enable proxy to reset only on power good. */ in e1000_suspend_workarounds_ich8lan()
5384 /* Set bit enable LPI (EEE) to reset only on in e1000_suspend_workarounds_ich8lan()
5405 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5410 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5413 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5417 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5420 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5424 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5429 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5432 * During Sx to S0 transitions on non-managed devices or managed devices
5442 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5456 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5459 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5492 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5497 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5504 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5507 ew32(LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5512 * e1000_led_on_ich8lan - Turn LEDs on
5519 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5523 ew32(LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5528 * e1000_led_off_ich8lan - Turn LEDs off
5535 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5540 ew32(LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5545 * e1000_setup_led_pchlan - Configures SW controllable LED
5552 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5556 * e1000_cleanup_led_pchlan - Restore the default LED operation
5563 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5567 * e1000_led_on_pchlan - Turn LEDs on
5574 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5597 * e1000_led_off_pchlan - Turn LEDs off
5604 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
5627 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5631 * and configure the PHY through s/w for EEPROM-less parts.
5633 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5634 * config done bit, so only an error is logged and continues. If we were
5635 * to return with error, EEPROM-less silicon would not be able to be reset
5647 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
5666 e_dbg("PHY Reset Asserted not set - needs delay\n"); in e1000_get_cfg_done_ich8lan()
5669 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
5671 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
5678 ret_val = -E1000_ERR_CONFIG; in e1000_get_cfg_done_ich8lan()
5686 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5695 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
5696 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
5701 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5729 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
5730 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
5731 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
5732 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
5733 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
5736 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
5740 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5741 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5742 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5743 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5744 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5745 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5746 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5747 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5748 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5749 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5750 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5751 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5752 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5753 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5755 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()
5760 /* check_mng_mode dependent on mac type */
5762 /* cleanup_led dependent on mac type */
5767 /* led_on dependent on mac type */
5768 /* led_off dependent on mac type */
5774 /* id_led_init dependent on mac type */
5817 .mac = e1000_ich8lan,
5833 .mac = e1000_ich9lan,
5850 .mac = e1000_ich10lan,
5867 .mac = e1000_pchlan,
5886 .mac = e1000_pch2lan,
5907 .mac = e1000_pch_lpt,
5928 .mac = e1000_pch_spt,
5948 .mac = e1000_pch_cnp,