Lines Matching full:phy
3 * drivers/net/ethernet/ibm/emac/phy.c
5 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
30 #include "phy.h"
35 static inline int _phy_read(struct mii_phy *phy, int reg) in _phy_read() argument
37 return phy->mdio_read(phy->dev, phy->address, reg); in _phy_read()
40 static inline void _phy_write(struct mii_phy *phy, int reg, int val) in _phy_write() argument
42 phy->mdio_write(phy->dev, phy->address, reg, val); in _phy_write()
45 static inline int gpcs_phy_read(struct mii_phy *phy, int reg) in gpcs_phy_read() argument
47 return phy->mdio_read(phy->dev, phy->gpcs_address, reg); in gpcs_phy_read()
50 static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val) in gpcs_phy_write() argument
52 phy->mdio_write(phy->dev, phy->gpcs_address, reg, val); in gpcs_phy_write()
55 int emac_mii_reset_phy(struct mii_phy *phy) in emac_mii_reset_phy() argument
60 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
68 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
79 int emac_mii_reset_gpcs(struct mii_phy *phy) in emac_mii_reset_gpcs() argument
84 val = gpcs_phy_read(phy, MII_BMCR); in emac_mii_reset_gpcs()
87 gpcs_phy_write(phy, MII_BMCR, val); in emac_mii_reset_gpcs()
92 val = gpcs_phy_read(phy, MII_BMCR); in emac_mii_reset_gpcs()
98 gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_gpcs()
100 if (limit > 0 && phy->mode == PHY_INTERFACE_MODE_SGMII) { in emac_mii_reset_gpcs()
102 gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */ in emac_mii_reset_gpcs()
103 gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */ in emac_mii_reset_gpcs()
104 gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */ in emac_mii_reset_gpcs()
110 static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise) in genmii_setup_aneg() argument
114 phy->autoneg = AUTONEG_ENABLE; in genmii_setup_aneg()
115 phy->speed = SPEED_10; in genmii_setup_aneg()
116 phy->duplex = DUPLEX_HALF; in genmii_setup_aneg()
117 phy->pause = phy->asym_pause = 0; in genmii_setup_aneg()
118 phy->advertising = advertise; in genmii_setup_aneg()
120 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
125 /* First clear the PHY */ in genmii_setup_aneg()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
129 adv = phy_read(phy, MII_ADVERTISE); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
148 if (phy->features & in genmii_setup_aneg()
150 adv = phy_read(phy, MII_CTRL1000); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
162 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
169 static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd) in genmii_setup_forced() argument
173 phy->autoneg = AUTONEG_DISABLE; in genmii_setup_forced()
174 phy->speed = speed; in genmii_setup_forced()
175 phy->duplex = fd; in genmii_setup_forced()
176 phy->pause = phy->asym_pause = 0; in genmii_setup_forced()
178 ctl = phy_read(phy, MII_BMCR); in genmii_setup_forced()
183 /* First clear the PHY */ in genmii_setup_forced()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
206 static int genmii_poll_link(struct mii_phy *phy) in genmii_poll_link() argument
211 phy_read(phy, MII_BMSR); in genmii_poll_link()
212 status = phy_read(phy, MII_BMSR); in genmii_poll_link()
215 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE)) in genmii_poll_link()
220 static int genmii_read_link(struct mii_phy *phy) in genmii_read_link() argument
222 if (phy->autoneg == AUTONEG_ENABLE) { in genmii_read_link()
224 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE); in genmii_read_link()
228 if (phy->features & in genmii_read_link()
230 int adv = phy_read(phy, MII_CTRL1000); in genmii_read_link()
231 glpa = phy_read(phy, MII_STAT1000); in genmii_read_link()
239 phy->speed = SPEED_10; in genmii_read_link()
240 phy->duplex = DUPLEX_HALF; in genmii_read_link()
241 phy->pause = phy->asym_pause = 0; in genmii_read_link()
244 phy->speed = SPEED_1000; in genmii_read_link()
246 phy->duplex = DUPLEX_FULL; in genmii_read_link()
248 phy->speed = SPEED_100; in genmii_read_link()
250 phy->duplex = DUPLEX_FULL; in genmii_read_link()
252 phy->duplex = DUPLEX_FULL; in genmii_read_link()
254 if (phy->duplex == DUPLEX_FULL) { in genmii_read_link()
255 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; in genmii_read_link()
256 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; in genmii_read_link()
259 int bmcr = phy_read(phy, MII_BMCR); in genmii_read_link()
264 phy->duplex = DUPLEX_FULL; in genmii_read_link()
266 phy->duplex = DUPLEX_HALF; in genmii_read_link()
268 phy->speed = SPEED_1000; in genmii_read_link()
270 phy->speed = SPEED_100; in genmii_read_link()
272 phy->speed = SPEED_10; in genmii_read_link()
274 phy->pause = phy->asym_pause = 0; in genmii_read_link()
306 static int cis8201_init(struct mii_phy *phy) in cis8201_init() argument
310 epcr = phy_read(phy, MII_CIS8201_EPCR); in cis8201_init()
316 switch (phy->mode) { in cis8201_init()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
334 phy_write(phy, MII_CIS8201_ACSR, in cis8201_init()
335 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT); in cis8201_init()
338 phy_write(phy, MII_CIS8201_10BTCSR, in cis8201_init()
339 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE); in cis8201_init()
367 static int m88e1111_init(struct mii_phy *phy) in m88e1111_init() argument
370 phy_write(phy, 0x14, 0x0ce3); in m88e1111_init()
371 phy_write(phy, 0x18, 0x4101); in m88e1111_init()
372 phy_write(phy, 0x09, 0x0e00); in m88e1111_init()
373 phy_write(phy, 0x04, 0x01e1); in m88e1111_init()
374 phy_write(phy, 0x00, 0x9140); in m88e1111_init()
375 phy_write(phy, 0x00, 0x1140); in m88e1111_init()
380 static int m88e1112_init(struct mii_phy *phy) in m88e1112_init() argument
383 * Marvell 88E1112 PHY needs to have the SGMII MAC in m88e1112_init()
393 phy_write(phy, 0x16, 0x0002); in m88e1112_init()
395 phy_write(phy, 0x00, 0x0040); /* 1Gbps */ in m88e1112_init()
396 reg_short = (u16)(phy_read(phy, 0x1a)); in m88e1112_init()
398 phy_write(phy, 0x1a, reg_short); in m88e1112_init()
399 emac_mii_reset_phy(phy); /* reset MAC interface */ in m88e1112_init()
402 phy_write(phy, 0x16, 0x0000); in m88e1112_init()
407 static int et1011c_init(struct mii_phy *phy) in et1011c_init() argument
411 reg_short = (u16)(phy_read(phy, 0x16)); in et1011c_init()
414 phy_write(phy, 0x16, reg_short); in et1011c_init()
416 reg_short = (u16)(phy_read(phy, 0x17)); in et1011c_init()
418 phy_write(phy, 0x17, reg_short); in et1011c_init()
420 phy_write(phy, 0x1c, 0x74f0); in et1011c_init()
474 static int ar8035_init(struct mii_phy *phy) in ar8035_init() argument
476 phy_write(phy, 0x1d, 0x5); /* Address debug register 5 */ in ar8035_init()
477 phy_write(phy, 0x1e, 0x2d47); /* Value copied from u-boot */ in ar8035_init()
478 phy_write(phy, 0x1d, 0xb); /* Address hib ctrl */ in ar8035_init()
479 phy_write(phy, 0x1e, 0xbc20); /* Value copied from u-boot */ in ar8035_init()
510 int emac_mii_phy_probe(struct mii_phy *phy, int address) in emac_mii_phy_probe() argument
516 phy->autoneg = AUTONEG_DISABLE; in emac_mii_phy_probe()
517 phy->advertising = 0; in emac_mii_phy_probe()
518 phy->address = address; in emac_mii_phy_probe()
519 phy->speed = SPEED_10; in emac_mii_phy_probe()
520 phy->duplex = DUPLEX_HALF; in emac_mii_phy_probe()
521 phy->pause = phy->asym_pause = 0; in emac_mii_phy_probe()
523 /* Take PHY out of isolate mode and reset it. */ in emac_mii_phy_probe()
524 if (emac_mii_reset_phy(phy)) in emac_mii_phy_probe()
528 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2); in emac_mii_phy_probe()
536 phy->def = def; in emac_mii_phy_probe()
538 /* Determine PHY features if needed */ in emac_mii_phy_probe()
539 phy->features = def->features; in emac_mii_phy_probe()
540 if (!phy->features) { in emac_mii_phy_probe()
541 u16 bmsr = phy_read(phy, MII_BMSR); in emac_mii_phy_probe()
543 phy->features |= SUPPORTED_Autoneg; in emac_mii_phy_probe()
545 phy->features |= SUPPORTED_10baseT_Half; in emac_mii_phy_probe()
547 phy->features |= SUPPORTED_10baseT_Full; in emac_mii_phy_probe()
549 phy->features |= SUPPORTED_100baseT_Half; in emac_mii_phy_probe()
551 phy->features |= SUPPORTED_100baseT_Full; in emac_mii_phy_probe()
553 u16 esr = phy_read(phy, MII_ESTATUS); in emac_mii_phy_probe()
555 phy->features |= SUPPORTED_1000baseT_Full; in emac_mii_phy_probe()
557 phy->features |= SUPPORTED_1000baseT_Half; in emac_mii_phy_probe()
559 phy->features |= SUPPORTED_MII; in emac_mii_phy_probe()
563 phy->advertising = phy->features; in emac_mii_phy_probe()