198 	u32 rctrl;		/* 0x050 Receive control register */  member
446 	iowrite32be(tmp, &regs->rctrl);  in init()
758 				iowrite32be(ioread32be(&regs->rctrl) |  in dtsec_isr()
759 					    RCTRL_GRS, &regs->rctrl);  in dtsec_isr()
871 		iowrite32be(ioread32be(&regs->rctrl) &  in graceful_start()
872 				~RCTRL_GRS, &regs->rctrl);  in graceful_start()
882 		tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;  in graceful_stop()
883 		iowrite32be(tmp, &regs->rctrl);  in graceful_stop()
965 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_set_tx_pause_frames()
1006 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_accept_rx_pause_frames()
1033 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_modify_mac_address()
1065 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_add_hash_mac_address()
1125 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_allmulti()
1131 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_allmulti()
1139 	u32 rctrl, tctrl;  in dtsec_set_tstamp()  local
1144 	rctrl = ioread32be(&regs->rctrl);  in dtsec_set_tstamp()
1148 		rctrl |= RCTRL_RTSE;  in dtsec_set_tstamp()
1151 		rctrl &= ~RCTRL_RTSE;  in dtsec_set_tstamp()
1155 	iowrite32be(rctrl, &regs->rctrl);  in dtsec_set_tstamp()
1176 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_del_hash_mac_address()
1241 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1247 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1250 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1256 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1270 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_adjust_link()