2  * Copyright 2008-2015 Freescale Semiconductor Inc.
54 #define TBICON_AN_SENSE		0x0100	/* Auto-negotiation sense enable */
192 	u32 tmr_ctrl;		/* 0x020 Time-stamp Control register */
193 	u32 tmr_pevent;		/* 0x024 Time-stamp event register */
200 	u32 igaddr[8];		/* 0x080-0x09C Individual/group address */
201 	u32 gaddr[8];		/* 0x0A0-0x0BC Group address registers 0-7 */
206 	u32 hafdup;		/* 0x10C Half-duplex */
213 		u32 exact_match1;	/* octets 1-4 */
214 		u32 exact_match2;	/* octets 5-6 */
215 	} macaddr[15];		/* 0x148-0x1BC mac exact match addresses 1-15 */
269 /* struct dtsec_cfg - dTSEC configuration
270  * Transmit half-duplex flow control, under software control for 10/100-Mbps
271  * half-duplex media. If set, back pressure is applied to media by raising
280  * standard 512-bit slot time window. If collisions are detected after this
292  * start-of-frame delimiter byte. The default value of 0x7 should be used in
295  * Packet alignment padding length. The specified number of bytes (1-31)
352 	cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;  in set_dflts()
353 	cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;  in set_dflts()
354 	cfg->tx_pad_crc = true;  in set_dflts()
355 	cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;  in set_dflts()
357 	cfg->rx_prepend = DEFAULT_RX_PREPEND;  in set_dflts()
358 	cfg->ptp_tsu_en = true;  in set_dflts()
359 	cfg->ptp_exception_en = true;  in set_dflts()
360 	cfg->preamble_len = DEFAULT_PREAMBLE_LEN;  in set_dflts()
361 	cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;  in set_dflts()
362 	cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;  in set_dflts()
363 	cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;  in set_dflts()
364 	cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;  in set_dflts()
365 	cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;  in set_dflts()
366 	cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;  in set_dflts()
375 	iowrite32be(tmp, &regs->macstnaddr1);  in set_mac_address()
378 	iowrite32be(tmp, &regs->macstnaddr2);  in set_mac_address()
391 	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);  in init()
392 	iowrite32be(0, &regs->maccfg1);  in init()
395 	tmp = ioread32be(&regs->tsec_id2);  in init()
404 			return -EINVAL;  in init()
409 			return -EINVAL;  in init()
431 	iowrite32be(tmp, &regs->ecntrl);  in init()
435 	if (cfg->tx_pause_time)  in init()
436 		tmp |= cfg->tx_pause_time;  in init()
437 	if (cfg->tx_pause_time_extd)  in init()
438 		tmp |= cfg->tx_pause_time_extd << PTV_PTE_SHIFT;  in init()
439 	iowrite32be(tmp, &regs->ptv);  in init()
442 	tmp |= (cfg->rx_prepend << RCTRL_PAL_SHIFT) & RCTRL_PAL_MASK;  in init()
446 	iowrite32be(tmp, &regs->rctrl);  in init()
452 	iowrite32be(tbi_addr, &regs->tbipa);  in init()
454 	iowrite32be(0, &regs->tmr_ctrl);  in init()
456 	if (cfg->ptp_tsu_en) {  in init()
459 		iowrite32be(tmp, &regs->tmr_pevent);  in init()
461 		if (cfg->ptp_exception_en) {  in init()
464 			iowrite32be(tmp, &regs->tmr_pemask);  in init()
471 	iowrite32be(tmp, &regs->maccfg1);  in init()
480 	tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &  in init()
482 	if (cfg->tx_pad_crc)  in init()
486 	iowrite32be(tmp, &regs->maccfg2);  in init()
488 	tmp = (((cfg->non_back_to_back_ipg1 <<  in init()
491 	       | ((cfg->non_back_to_back_ipg2 <<  in init()
494 	       | ((cfg->min_ifg_enforcement << IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)  in init()
496 	       | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));  in init()
497 	iowrite32be(tmp, &regs->ipgifg);  in init()
501 	tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)  in init()
503 	tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);  in init()
505 	iowrite32be(tmp, &regs->hafdup);  in init()
508 	iowrite32be(cfg->maximum_frame, &regs->maxfrm);  in init()
510 	iowrite32be(0xffffffff, &regs->cam1);  in init()
511 	iowrite32be(0xffffffff, &regs->cam2);  in init()
513 	iowrite32be(exception_mask, &regs->imask);  in init()
515 	iowrite32be(0xffffffff, &regs->ievent);  in init()
525 		iowrite32be(0, &regs->igaddr[i]);  in init()
527 		iowrite32be(0, &regs->gaddr[i]);  in init()
542 		reg = &regs->gaddr[reg_idx - 8];  in set_bucket()
544 		reg = &regs->igaddr[reg_idx];  in set_bucket()
554 	if (dtsec->max_speed >= SPEED_10000) {  in check_init_parameters()
556 		return -EINVAL;  in check_init_parameters()
558 	if ((dtsec->dtsec_drv_param)->rx_prepend >  in check_init_parameters()
562 		return -EINVAL;  in check_init_parameters()
564 	if (((dtsec->dtsec_drv_param)->non_back_to_back_ipg1 >  in check_init_parameters()
566 	    ((dtsec->dtsec_drv_param)->non_back_to_back_ipg2 >  in check_init_parameters()
568 	     ((dtsec->dtsec_drv_param)->back_to_back_ipg >  in check_init_parameters()
572 		return -EINVAL;  in check_init_parameters()
574 	if ((dtsec->dtsec_drv_param)->halfdup_retransmit >  in check_init_parameters()
578 		return -EINVAL;  in check_init_parameters()
580 	if ((dtsec->dtsec_drv_param)->halfdup_coll_window >  in check_init_parameters()
584 		return -EINVAL;  in check_init_parameters()
589 	if (!dtsec->exception_cb) {  in check_init_parameters()
591 		return -EINVAL;  in check_init_parameters()
593 	if (!dtsec->event_cb) {  in check_init_parameters()
595 		return -EINVAL;  in check_init_parameters()
670 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_get_max_frame_length()
672 	if (is_init_done(dtsec->dtsec_drv_param))  in dtsec_get_max_frame_length()
675 	return (u16)ioread32be(&regs->maxfrm);  in dtsec_get_max_frame_length()
681 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_isr()
685 	event = ioread32be(&regs->ievent) &  in dtsec_isr()
688 	event &= ioread32be(&regs->imask);  in dtsec_isr()
690 	iowrite32be(event, &regs->ievent);  in dtsec_isr()
693 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_RX);  in dtsec_isr()
695 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_RX_CTL);  in dtsec_isr()
697 		dtsec->exception_cb(dtsec->dev_id,  in dtsec_isr()
700 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_TX);  in dtsec_isr()
702 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_CTL);  in dtsec_isr()
704 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_ERR);  in dtsec_isr()
706 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_LATE_COL);  in dtsec_isr()
708 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);  in dtsec_isr()
711 		if (dtsec->fm_rev_info.major == 2) {  in dtsec_isr()
717 			tpkt1 = ioread32be(&regs->tpkt);  in dtsec_isr()
720 			tmp_reg1 = ioread32be(&regs->reserved02c0[27]);  in dtsec_isr()
741 			tpkt2 = ioread32be(&regs->tpkt);  in dtsec_isr()
742 			tmp_reg2 = ioread32be(&regs->reserved02c0[27]);  in dtsec_isr()
758 				iowrite32be(ioread32be(&regs->rctrl) |  in dtsec_isr()
759 					    RCTRL_GRS, &regs->rctrl);  in dtsec_isr()
765 					if (ioread32be(&regs->ievent) &  in dtsec_isr()
770 				if (ioread32be(&regs->ievent) &  in dtsec_isr()
773 						    &regs->ievent);  in dtsec_isr()
780 				fman_reset_mac(dtsec->fm, dtsec->mac_id);  in dtsec_isr()
791 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_FIFO_UNDRN);  in dtsec_isr()
794 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_MAG_PCKT);  in dtsec_isr()
796 		dtsec->exception_cb(dtsec->dev_id,  in dtsec_isr()
799 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_DATA_ERR);  in dtsec_isr()
801 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_1G_RX_DATA_ERR);  in dtsec_isr()
811 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_1588_isr()
814 	if (dtsec->ptp_tsu_enabled) {  in dtsec_1588_isr()
815 		event = ioread32be(&regs->tmr_pevent);  in dtsec_1588_isr()
816 		event &= ioread32be(&regs->tmr_pemask);  in dtsec_1588_isr()
819 			iowrite32be(event, &regs->tmr_pevent);  in dtsec_1588_isr()
821 			dtsec->exception_cb(dtsec->dev_id,  in dtsec_1588_isr()
829 	fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,  in free_init_resources()
831 	fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,  in free_init_resources()
835 	free_hash_table(dtsec->multicast_addr_hash);  in free_init_resources()
836 	dtsec->multicast_addr_hash = NULL;  in free_init_resources()
839 	free_hash_table(dtsec->unicast_addr_hash);  in free_init_resources()
840 	dtsec->unicast_addr_hash = NULL;  in free_init_resources()
845 	if (is_init_done(dtsec->dtsec_drv_param))  in dtsec_cfg_max_frame_len()
846 		return -EINVAL;  in dtsec_cfg_max_frame_len()
848 	dtsec->dtsec_drv_param->maximum_frame = new_val;  in dtsec_cfg_max_frame_len()
855 	if (is_init_done(dtsec->dtsec_drv_param))  in dtsec_cfg_pad_and_crc()
856 		return -EINVAL;  in dtsec_cfg_pad_and_crc()
858 	dtsec->dtsec_drv_param->tx_pad_crc = new_val;  in dtsec_cfg_pad_and_crc()
865 	struct dtsec_regs __iomem *regs = dtsec->regs;  in graceful_start()
868 		iowrite32be(ioread32be(&regs->tctrl) &  in graceful_start()
869 				~TCTRL_GTS, &regs->tctrl);  in graceful_start()
871 		iowrite32be(ioread32be(&regs->rctrl) &  in graceful_start()
872 				~RCTRL_GRS, &regs->rctrl);  in graceful_start()
877 	struct dtsec_regs __iomem *regs = dtsec->regs;  in graceful_stop()
880 	/* Graceful stop - Assert the graceful Rx stop bit */  in graceful_stop()
882 		tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;  in graceful_stop()
883 		iowrite32be(tmp, &regs->rctrl);  in graceful_stop()
885 		if (dtsec->fm_rev_info.major == 2) {  in graceful_stop()
894 	/* Graceful stop - Assert the graceful Tx stop bit */  in graceful_stop()
896 		if (dtsec->fm_rev_info.major == 2) {  in graceful_stop()
900 			tmp = ioread32be(&regs->tctrl) | TCTRL_GTS;  in graceful_stop()
901 			iowrite32be(tmp, &regs->tctrl);  in graceful_stop()
911 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_enable()
914 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_enable()
915 		return -EINVAL;  in dtsec_enable()
918 	tmp = ioread32be(&regs->maccfg1);  in dtsec_enable()
924 	iowrite32be(tmp, &regs->maccfg1);  in dtsec_enable()
926 	/* Graceful start - clear the graceful Rx/Tx stop bit */  in dtsec_enable()
934 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_disable()
937 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_disable()
938 		return -EINVAL;  in dtsec_disable()
940 	/* Graceful stop - Assert the graceful Rx/Tx stop bit */  in dtsec_disable()
943 	tmp = ioread32be(&regs->maccfg1);  in dtsec_disable()
949 	iowrite32be(tmp, &regs->maccfg1);  in dtsec_disable()
958 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_set_tx_pause_frames()
962 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_set_tx_pause_frames()
963 		return -EINVAL;  in dtsec_set_tx_pause_frames()
965 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_set_tx_pause_frames()
967 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_set_tx_pause_frames()
974 		if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {  in dtsec_set_tx_pause_frames()
975 			pr_warn("pause-time: %d illegal.Should be > 320\n",  in dtsec_set_tx_pause_frames()
977 			return -EINVAL;  in dtsec_set_tx_pause_frames()
980 		ptv = ioread32be(&regs->ptv);  in dtsec_set_tx_pause_frames()
983 		iowrite32be(ptv, &regs->ptv);  in dtsec_set_tx_pause_frames()
985 		/* trigger the transmission of a flow-control pause frame */  in dtsec_set_tx_pause_frames()
986 		iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,  in dtsec_set_tx_pause_frames()
987 			    &regs->maccfg1);  in dtsec_set_tx_pause_frames()
989 		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,  in dtsec_set_tx_pause_frames()
990 			    &regs->maccfg1);  in dtsec_set_tx_pause_frames()
999 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_accept_rx_pause_frames()
1003 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_accept_rx_pause_frames()
1004 		return -EINVAL;  in dtsec_accept_rx_pause_frames()
1006 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_accept_rx_pause_frames()
1008 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_accept_rx_pause_frames()
1013 	tmp = ioread32be(&regs->maccfg1);  in dtsec_accept_rx_pause_frames()
1018 	iowrite32be(tmp, &regs->maccfg1);  in dtsec_accept_rx_pause_frames()
1027 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_modify_mac_address()
1030 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_modify_mac_address()
1031 		return -EINVAL;  in dtsec_modify_mac_address()
1033 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_modify_mac_address()
1035 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_modify_mac_address()
1043 	dtsec->addr = ENET_ADDR_TO_UINT64(*enet_addr);  in dtsec_modify_mac_address()
1044 	set_mac_address(dtsec->regs, (u8 *)(*enet_addr));  in dtsec_modify_mac_address()
1053 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_add_hash_mac_address()
1060 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_add_hash_mac_address()
1061 		return -EINVAL;  in dtsec_add_hash_mac_address()
1065 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_add_hash_mac_address()
1071 		return -EINVAL;  in dtsec_add_hash_mac_address()
1097 	set_bucket(dtsec->regs, bucket, true);  in dtsec_add_hash_mac_address()
1102 		return -ENOMEM;  in dtsec_add_hash_mac_address()
1103 	hash_entry->addr = addr;  in dtsec_add_hash_mac_address()
1104 	INIT_LIST_HEAD(&hash_entry->node);  in dtsec_add_hash_mac_address()
1108 		list_add_tail(&hash_entry->node,  in dtsec_add_hash_mac_address()
1109 			      &dtsec->multicast_addr_hash->lsts[bucket]);  in dtsec_add_hash_mac_address()
1111 		list_add_tail(&hash_entry->node,  in dtsec_add_hash_mac_address()
1112 			      &dtsec->unicast_addr_hash->lsts[bucket]);  in dtsec_add_hash_mac_address()
1120 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_set_allmulti()
1122 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_set_allmulti()
1123 		return -EINVAL;  in dtsec_set_allmulti()
1125 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_allmulti()
1131 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_allmulti()
1138 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_set_tstamp()
1141 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_set_tstamp()
1142 		return -EINVAL;  in dtsec_set_tstamp()
1144 	rctrl = ioread32be(&regs->rctrl);  in dtsec_set_tstamp()
1145 	tctrl = ioread32be(&regs->tctrl);  in dtsec_set_tstamp()
1155 	iowrite32be(rctrl, &regs->rctrl);  in dtsec_set_tstamp()
1156 	iowrite32be(tctrl, &regs->tctrl);  in dtsec_set_tstamp()
1163 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_del_hash_mac_address()
1171 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_del_hash_mac_address()
1172 		return -EINVAL;  in dtsec_del_hash_mac_address()
1176 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_del_hash_mac_address()
1182 		return -EINVAL;  in dtsec_del_hash_mac_address()
1201 			      &dtsec->multicast_addr_hash->lsts[bucket]) {  in dtsec_del_hash_mac_address()
1203 			if (hash_entry && hash_entry->addr == addr) {  in dtsec_del_hash_mac_address()
1204 				list_del_init(&hash_entry->node);  in dtsec_del_hash_mac_address()
1209 		if (list_empty(&dtsec->multicast_addr_hash->lsts[bucket]))  in dtsec_del_hash_mac_address()
1210 			set_bucket(dtsec->regs, bucket, false);  in dtsec_del_hash_mac_address()
1214 			      &dtsec->unicast_addr_hash->lsts[bucket]) {  in dtsec_del_hash_mac_address()
1216 			if (hash_entry && hash_entry->addr == addr) {  in dtsec_del_hash_mac_address()
1217 				list_del_init(&hash_entry->node);  in dtsec_del_hash_mac_address()
1222 		if (list_empty(&dtsec->unicast_addr_hash->lsts[bucket]))  in dtsec_del_hash_mac_address()
1223 			set_bucket(dtsec->regs, bucket, false);  in dtsec_del_hash_mac_address()
1234 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_set_promiscuous()
1237 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_set_promiscuous()
1238 		return -EINVAL;  in dtsec_set_promiscuous()
1241 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1247 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1250 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1256 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1263 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_adjust_link()
1267 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_adjust_link()
1268 		return -EINVAL;  in dtsec_adjust_link()
1270 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_adjust_link()
1272 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_adjust_link()
1277 	tmp = ioread32be(&regs->maccfg2);  in dtsec_adjust_link()
1287 	iowrite32be(tmp, &regs->maccfg2);  in dtsec_adjust_link()
1289 	tmp = ioread32be(&regs->ecntrl);  in dtsec_adjust_link()
1294 	iowrite32be(tmp, &regs->ecntrl);  in dtsec_adjust_link()
1305 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_restart_autoneg()
1306 		return -EINVAL;  in dtsec_restart_autoneg()
1308 	tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);  in dtsec_restart_autoneg()
1314 	phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);  in dtsec_restart_autoneg()
1321 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_get_version()
1323 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_get_version()
1324 		return -EINVAL;  in dtsec_get_version()
1326 	*mac_version = ioread32be(&regs->tsec_id);  in dtsec_get_version()
1334 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_set_exception()
1337 	if (!is_init_done(dtsec->dtsec_drv_param))  in dtsec_set_exception()
1338 		return -EINVAL;  in dtsec_set_exception()
1344 				dtsec->exceptions |= bit_mask;  in dtsec_set_exception()
1346 				dtsec->exceptions &= ~bit_mask;  in dtsec_set_exception()
1349 			return -EINVAL;  in dtsec_set_exception()
1352 			iowrite32be(ioread32be(&regs->imask) | bit_mask,  in dtsec_set_exception()
1353 				    &regs->imask);  in dtsec_set_exception()
1355 			iowrite32be(ioread32be(&regs->imask) & ~bit_mask,  in dtsec_set_exception()
1356 				    &regs->imask);  in dtsec_set_exception()
1358 		if (!dtsec->ptp_tsu_enabled) {  in dtsec_set_exception()
1359 			pr_err("Exception valid for 1588 only\n");  in dtsec_set_exception()
1360 			return -EINVAL;  in dtsec_set_exception()
1365 				dtsec->en_tsu_err_exception = true;  in dtsec_set_exception()
1366 				iowrite32be(ioread32be(&regs->tmr_pemask) |  in dtsec_set_exception()
1368 					    &regs->tmr_pemask);  in dtsec_set_exception()
1370 				dtsec->en_tsu_err_exception = false;  in dtsec_set_exception()
1371 				iowrite32be(ioread32be(&regs->tmr_pemask) &  in dtsec_set_exception()
1373 					    &regs->tmr_pemask);  in dtsec_set_exception()
1378 			return -EINVAL;  in dtsec_set_exception()
1387 	struct dtsec_regs __iomem *regs = dtsec->regs;  in dtsec_init()
1392 	if (is_init_done(dtsec->dtsec_drv_param))  in dtsec_init()
1393 		return -EINVAL;  in dtsec_init()
1396 	    (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {  in dtsec_init()
1398 		return -EINVAL;  in dtsec_init()
1405 	dtsec_drv_param = dtsec->dtsec_drv_param;  in dtsec_init()
1407 	err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,  in dtsec_init()
1408 		   dtsec->max_speed, dtsec->addr, dtsec->exceptions,  in dtsec_init()
1409 		   dtsec->tbiphy->mdio.addr);  in dtsec_init()
1416 	if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {  in dtsec_init()
1421 		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);  in dtsec_init()
1424 		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);  in dtsec_init()
1428 		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);  in dtsec_init()
1430 		if (dtsec->basex_if)  in dtsec_init()
1434 		phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);  in dtsec_init()
1439 		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);  in dtsec_init()
1443 	max_frm_ln = (u16)ioread32be(&regs->maxfrm);  in dtsec_init()
1444 	err = fman_set_mac_max_frame(dtsec->fm, dtsec->mac_id, max_frm_ln);  in dtsec_init()
1448 		return -EINVAL;  in dtsec_init()
1451 	dtsec->multicast_addr_hash =  in dtsec_init()
1453 	if (!dtsec->multicast_addr_hash) {  in dtsec_init()
1456 		return -ENOMEM;  in dtsec_init()
1459 	dtsec->unicast_addr_hash = alloc_hash_table(DTSEC_HASH_TABLE_SIZE);  in dtsec_init()
1460 	if (!dtsec->unicast_addr_hash) {  in dtsec_init()
1463 		return -ENOMEM;  in dtsec_init()
1467 	fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,  in dtsec_init()
1469 	/* register 1588 intr handler for TMR to FPM (normal) */  in dtsec_init()
1470 	fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,  in dtsec_init()
1474 	dtsec->dtsec_drv_param = NULL;  in dtsec_init()
1483 	kfree(dtsec->dtsec_drv_param);  in dtsec_free()
1484 	dtsec->dtsec_drv_param = NULL;  in dtsec_free()
1496 	base_addr = params->base_addr;  in dtsec_config()
1509 	dtsec->dtsec_drv_param = dtsec_drv_param;  in dtsec_config()
1513 	dtsec->regs = base_addr;  in dtsec_config()
1514 	dtsec->addr = ENET_ADDR_TO_UINT64(params->addr);  in dtsec_config()
1515 	dtsec->max_speed = params->max_speed;  in dtsec_config()
1516 	dtsec->phy_if = params->phy_if;  in dtsec_config()
1517 	dtsec->mac_id = params->mac_id;  in dtsec_config()
1518 	dtsec->exceptions = (DTSEC_IMASK_BREN	|  in dtsec_config()
1531 	dtsec->exception_cb = params->exception_cb;  in dtsec_config()
1532 	dtsec->event_cb = params->event_cb;  in dtsec_config()
1533 	dtsec->dev_id = params->dev_id;  in dtsec_config()
1534 	dtsec->ptp_tsu_enabled = dtsec->dtsec_drv_param->ptp_tsu_en;  in dtsec_config()
1535 	dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;  in dtsec_config()
1537 	dtsec->fm = params->fm;  in dtsec_config()
1538 	dtsec->basex_if = params->basex_if;  in dtsec_config()
1540 	if (!params->internal_phy_node) {  in dtsec_config()
1545 	dtsec->tbiphy = of_phy_find_device(params->internal_phy_node);  in dtsec_config()
1546 	if (!dtsec->tbiphy) {  in dtsec_config()
1551 	put_device(&dtsec->tbiphy->mdio.dev);  in dtsec_config()
1554 	fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);  in dtsec_config()