Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
43 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
44 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
45 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
46 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
47 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
48 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
75 #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
76 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
77 #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
78 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
88 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */
89 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
90 #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
91 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
92 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
93 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
94 #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
95 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
96 #define RMON_T_COL 0x224 /* RMON TX collision count */
97 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
98 #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
99 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
100 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
101 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
102 #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
103 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
104 #define RMON_T_OCTETS 0x244 /* RMON TX octets */
106 #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
107 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
108 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
109 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
110 #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
111 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
112 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
113 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
114 #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
115 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
116 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
117 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */
118 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
119 #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
120 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
121 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
122 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
123 #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
124 #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
126 #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
127 #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
128 #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
129 #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
130 #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
131 #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
132 #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
133 #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
135 #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
136 #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
137 #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
139 #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
140 #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
300 * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
335 /* The number of Tx and Rx buffers. These are allocated from the page
393 /* Controller is ENET-MAC */
395 /* Controller needs driver to swap frame */
413 * frames not being transmitted until there is a 0-to-1 transition on
420 * - Two class indicators on receive with configurable priority
421 * - Two class indicators and line speed timer on transmit allowing
423 * - Additional DMA registers provisioned to allow managing up to 3
428 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
436 * The wait-time-cycles is at least 6 clock cycles of the slower clock between
438 * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
467 /* Address of Rx and Tx buffers */
527 /* The saved address of a sent-in-place packet/buffer, for skfree(). */