Lines Matching +full:full +full:- +full:frame

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
35 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
65 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
68 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
69 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
154 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
161 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
363 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
364 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
365 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
367 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
368 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
369 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
387 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
393 /* Controller is ENET-MAC */
395 /* Controller needs driver to swap frame */
410  * detected as not set during a prior frame transmission, then the
413  * frames not being transmitted until there is a 0-to-1 transition on
420  * - Two class indicators on receive with configurable priority
421  * - Two class indicators and line speed timer on transmit allowing
423  * - Additional DMA registers provisioned to allow managing up to 3
428  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
436  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
438  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
507  * empty and completely full conditions.  The empty/ready indicator in
527 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */