Lines Matching +full:0 +full:x7c00
19 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 #define MPU_MAILBOX_DB_OFFSET 0x160
25 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
28 #define MPU_EP_CONTROL 0
31 #define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
32 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
34 #define POST_STAGE_MASK 0x0000FFFF
35 #define POST_ERR_MASK 0x1
37 #define POST_ERR_RECOVERY_CODE_MASK 0xFFF
40 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
43 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
47 #define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */
49 #define POST_STAGE_FAT_LOG_START 0x0D00
50 #define POST_STAGE_ARMFW_UE 0xF000 /*FW has asserted an UE*/
53 #define SLIPORT_STATUS_OFFSET 0x404
54 #define SLIPORT_CONTROL_OFFSET 0x408
55 #define SLIPORT_ERROR1_OFFSET 0x40C
56 #define SLIPORT_ERROR2_OFFSET 0x410
57 #define PHYSDEV_CONTROL_OFFSET 0x414
59 #define SLIPORT_STATUS_ERR_MASK 0x80000000
60 #define SLIPORT_STATUS_DIP_MASK 0x02000000
61 #define SLIPORT_STATUS_RN_MASK 0x01000000
62 #define SLIPORT_STATUS_RDY_MASK 0x00800000
63 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
64 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
65 #define PHYSDEV_CONTROL_DD_MASK 0x00000004
66 #define PHYSDEV_CONTROL_INP_MASK 0x40000000
68 #define SLIPORT_ERROR_NO_RESOURCE1 0x2
69 #define SLIPORT_ERROR_NO_RESOURCE2 0x9
71 #define SLIPORT_ERROR_FW_RESET1 0x2
72 #define SLIPORT_ERROR_FW_RESET2 0x0
75 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
85 #define BE_FUNCTION_CAPS_RSS 0x2
86 #define BE_FUNCTION_CAPS_SUPER_NIC 0x40
89 #define PCICFG_PM_CONTROL_OFFSET 0x44
90 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
93 #define PCICFG_ONLINE0 0xB0
94 #define PCICFG_ONLINE1 0xB4
97 #define PCICFG_UE_STATUS_LOW 0xA0
98 #define PCICFG_UE_STATUS_HIGH 0xA4
99 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
100 #define PCICFG_UE_STATUS_HI_MASK 0xAC
103 #define SLI_INTF_REG_OFFSET 0x58
104 #define SLI_INTF_VALID_MASK 0xE0000000
105 #define SLI_INTF_VALID 0xC0000000
106 #define SLI_INTF_HINT2_MASK 0x1F000000
108 #define SLI_INTF_HINT1_MASK 0x00FF0000
110 #define SLI_INTF_FAMILY_MASK 0x00000F00
112 #define SLI_INTF_IF_TYPE_MASK 0x0000F000
114 #define SLI_INTF_REV_MASK 0x000000F0
116 #define SLI_INTF_FT_MASK 0x00000001
122 #define CEV_ISR0_OFFSET 0xC18
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
147 #define R2I_DLY_ENC_0 0 /* No delay */
153 #define DB_CQ_OFFSET 0x120
154 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
155 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
165 #define DB_TXULP1_OFFSET 0x60
166 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
169 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
172 #define DB_RQ_OFFSET 0x100
173 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
178 #define DB_MCCQ_OFFSET 0x140
179 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
187 #define RETRIEVE_FAT 0
191 #define BE_UNICAST_PACKET 0
201 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
202 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
210 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
212 __le32 frag_pa_hi; /* dword 0 */
215 __le32 frag_len; /* dword 3: bits 0 - 15 */
222 u8 rsvd0[32]; /* dword 0 */
245 #define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */
252 #define BE_TX_COMP_HDR_PARSE_ERR 0x2
253 #define BE_TX_COMP_NDMA_ERR 0x3
254 #define BE_TX_COMP_ACL_ERR 0x5
256 #define LANCER_TX_COMP_LSO_ERR 0x1
257 #define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3
258 #define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5
259 #define LANCER_TX_COMP_QINQ_ERR 0x7
260 #define LANCER_TX_COMP_SGE_ERR 0x9
261 #define LANCER_TX_COMP_PARITY_ERR 0xb
262 #define LANCER_TX_COMP_DMA_ERR 0xd
270 u8 wrb_index[16]; /* dword 0 */
271 u8 ct[2]; /* dword 0 */
272 u8 port[2]; /* dword 0 */
273 u8 rsvd0[8]; /* dword 0 */
274 u8 status[4]; /* dword 0 */
303 u8 vlan_tag[16]; /* dword 0 */
304 u8 pktsize[14]; /* dword 0 */
305 u8 port; /* dword 0 */
306 u8 ip_opt; /* dword 0 */
337 u8 vlan_tag[16]; /* dword 0 */
338 u8 pktsize[14]; /* dword 0 */
339 u8 vtp; /* dword 0 */
340 u8 ip_opt; /* dword 0 */