Lines Matching +full:0 +full:xd00000
28 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
29 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
30 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
32 u32 embedded; /* dword 0 */
50 MCC_STATUS_SUCCESS = 0,
63 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
64 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
65 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
66 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
67 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
68 MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57,
69 MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES = 0x60
72 #define CQE_BASE_STATUS_MASK 0xFFFF
73 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */
74 #define CQE_ADDL_STATUS_MASK 0xFF
79 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
82 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
83 CQE_ADDL_STATUS_MASK : 0))
86 u32 status; /* dword 0 */
96 #define ASYNC_EVENT_CODE_MASK 0xFF
98 #define ASYNC_EVENT_TYPE_MASK 0xFF
99 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
100 #define ASYNC_EVENT_CODE_GRP_5 0x5
101 #define ASYNC_EVENT_QOS_SPEED 0x1
102 #define ASYNC_EVENT_COS_PRIORITY 0x2
103 #define ASYNC_EVENT_PVID_STATE 0x3
104 #define ASYNC_EVENT_CODE_QNQ 0x6
106 #define ASYNC_EVENT_CODE_SLIPORT 0x11
107 #define ASYNC_EVENT_PORT_MISCONFIG 0x9
108 #define ASYNC_EVENT_FW_CONTROL 0x5
111 LINK_DOWN = 0x0,
112 LINK_UP = 0x1
114 #define LINK_STATUS_MASK 0x1
115 #define LOGICAL_LINK_STATUS_MASK 0x2
177 BE_PHY_FUNCTIONAL = 0,
185 #define PHY_STATE_MSG_SEVERITY 0x6
186 #define PHY_STATE_OPER 0x1
187 #define PHY_STATE_INFO_VALID 0x80
188 #define PHY_STATE_OPER_MSG_NONE 0x2
189 #define DEFAULT_MSG_SEVERITY 0x1
205 * phy state of port 0: bits 7 - 0
212 * phy state info of port 0: bits 7 - 0
218 * Link operability :bit 0
228 #define BMC_FILT_BROADCAST_ARP BIT(0)
249 #define CMD_SUBSYSTEM_COMMON 0x1
250 #define CMD_SUBSYSTEM_ETH 0x3
251 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
329 u8 opcode; /* dword 0 */
330 u8 subsystem; /* dword 0 */
331 u8 port_number; /* dword 0 */
332 u8 domain; /* dword 0 */
339 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
342 u8 opcode; /* dword 0 */
343 u8 subsystem; /* dword 0 */
344 u8 rsvd[2]; /* dword 0 */
364 u8 cidx[13]; /* dword 0*/
365 u8 rsvd0[3]; /* dword 0*/
366 u8 epidx[13]; /* dword 0*/
367 u8 valid; /* dword 0*/
368 u8 rsvd1; /* dword 0*/
369 u8 size; /* dword 0*/
404 MAC_ADDRESS_TYPE_STORAGE = 0x0,
405 MAC_ADDRESS_TYPE_NETWORK = 0x1,
406 MAC_ADDRESS_TYPE_PD = 0x2,
407 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
452 u8 cidx[11]; /* dword 0*/
453 u8 rsvd0; /* dword 0*/
454 u8 coalescwm[2]; /* dword 0*/
455 u8 nodelay; /* dword 0*/
456 u8 epidx[11]; /* dword 0*/
457 u8 rsvd1; /* dword 0*/
458 u8 count[2]; /* dword 0*/
459 u8 valid; /* dword 0*/
460 u8 solevent; /* dword 0*/
461 u8 eventable; /* dword 0*/
475 u8 rsvd0[12]; /* dword 0*/
476 u8 coalescwm[2]; /* dword 0*/
477 u8 nodelay; /* dword 0*/
478 u8 rsvd1[12]; /* dword 0*/
479 u8 count[2]; /* dword 0*/
480 u8 valid; /* dword 0*/
481 u8 rsvd2; /* dword 0*/
482 u8 eventable; /* dword 0*/
643 BE_IF_FLAGS_RSS = 0x4,
644 BE_IF_FLAGS_PROMISCUOUS = 0x8,
645 BE_IF_FLAGS_BROADCAST = 0x10,
646 BE_IF_FLAGS_UNTAGGED = 0x20,
647 BE_IF_FLAGS_ULP = 0x40,
648 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
649 BE_IF_FLAGS_VLAN = 0x100,
650 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
651 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
652 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
653 BE_IF_FLAGS_MULTICAST = 0x1000,
654 BE_IF_FLAGS_DEFQ_RSS = 0x1000000
702 u32 rx_bytes_lsd; /* dword 0*/
795 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
1061 PHY_LINK_DUPLEX_NONE = 0x0,
1062 PHY_LINK_DUPLEX_HALF = 0x1,
1063 PHY_LINK_DUPLEX_FULL = 0x2
1067 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
1068 PHY_LINK_SPEED_10MBPS = 0x1,
1069 PHY_LINK_SPEED_100MBPS = 0x2,
1070 PHY_LINK_SPEED_1GBPS = 0x3,
1071 PHY_LINK_SPEED_10GBPS = 0x4,
1072 PHY_LINK_SPEED_20GBPS = 0x5,
1073 PHY_LINK_SPEED_25GBPS = 0x6,
1074 PHY_LINK_SPEED_40GBPS = 0x7
1099 TR_PAGE_A0 = 0xa0,
1100 TR_PAGE_A2 = 0xa2
1104 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83
1105 #define QSFP_PLUS_CR4_CABLE 0x8
1106 #define QSFP_PLUS_SR4_CABLE 0x4
1107 #define QSFP_PLUS_LR4_CABLE 0x2
1110 #define SFP_PLUS_SFF_8472_COMP 0x5E
1111 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8
1112 #define SFP_PLUS_COPPER_CABLE 0x4
1113 #define SFP_VENDOR_NAME_OFFSET 0x14
1114 #define SFP_VENDOR_PN_OFFSET 0x28
1173 #define RDMA_ENABLED 0x4
1174 #define QNQ_MODE 0x400
1175 #define VNIC_MODE 0x20000
1176 #define UMC_ENABLED 0x1000000
1204 #define RSS_ENABLE_NONE 0x0
1205 #define RSS_ENABLE_IPV4 0x1
1206 #define RSS_ENABLE_TCP_IPV4 0x2
1207 #define RSS_ENABLE_IPV6 0x4
1208 #define RSS_ENABLE_TCP_IPV6 0x8
1209 #define RSS_ENABLE_UDP_IPV4 0x10
1210 #define RSS_ENABLE_UDP_IPV6 0x20
1228 #define BEACON_STATE_ENABLED 0x1
1229 #define BEACON_STATE_DISABLED 0x0
1257 OPTYPE_ISCSI_ACTIVE = 0,
1277 BE2_BIOS_COMP_MAX_SIZE = 0x40000,
1278 BE2_REDBOOT_COMP_MAX_SIZE = 0x40000,
1279 BE2_COMP_MAX_SIZE = 0x140000
1284 BE3_NCSI_COMP_MAX_SIZE = 0x40000,
1285 BE3_PHY_FW_COMP_MAX_SIZE = 0x40000,
1286 BE3_BIOS_COMP_MAX_SIZE = 0x80000,
1287 BE3_REDBOOT_COMP_MAX_SIZE = 0x100000,
1288 BE3_COMP_MAX_SIZE = 0x200000
1293 BE2_REDBOOT_START = 0x8000,
1294 BE2_FCOE_BIOS_START = 0x80000,
1295 BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000,
1296 BE2_ISCSI_BACKUP_IMAGE_START = 0x240000,
1297 BE2_FCOE_PRIMARY_IMAGE_START = 0x380000,
1298 BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000,
1299 BE2_ISCSI_BIOS_START = 0x700000,
1300 BE2_PXE_BIOS_START = 0x780000
1305 BE3_REDBOOT_START = 0x40000,
1306 BE3_PHY_FW_START = 0x140000,
1307 BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000,
1308 BE3_ISCSI_BACKUP_IMAGE_START = 0x400000,
1309 BE3_FCOE_PRIMARY_IMAGE_START = 0x600000,
1310 BE3_FCOE_BACKUP_IMAGE_START = 0x800000,
1311 BE3_ISCSI_BIOS_START = 0xc00000,
1312 BE3_PXE_BIOS_START = 0xc80000,
1313 BE3_FCOE_BIOS_START = 0xd00000,
1314 BE3_NCSI_START = 0xf40000
1319 IMAGE_NCSI = 0x10,
1320 IMAGE_OPTION_ROM_PXE = 0x20,
1321 IMAGE_OPTION_ROM_FCOE = 0x21,
1322 IMAGE_OPTION_ROM_ISCSI = 0x22,
1323 IMAGE_FLASHISM_JUMPVECTOR = 0x30,
1324 IMAGE_FIRMWARE_ISCSI = 0xa0,
1325 IMAGE_FIRMWARE_FCOE = 0xa2,
1326 IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0,
1327 IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2,
1328 IMAGE_FIRMWARE_PHY = 0xc0,
1329 IMAGE_REDBOOT_DIR = 0xd0,
1330 IMAGE_REDBOOT_CONFIG = 0xd1,
1331 IMAGE_UFI_DIR = 0xd2,
1332 IMAGE_BOOT_CODE = 0xe2
1479 #define LANCER_NO_RESET_NEEDED 0x00
1480 #define LANCER_FW_RESET_NEEDED 0x02
1497 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1564 #define BE_WOL_CAP 0x1
1565 #define BE_PME_D0_CAP 0x8
1566 #define BE_PME_D1_CAP 0x10
1567 #define BE_PME_D2_CAP 0x20
1568 #define BE_PME_D3HOT_CAP 0x40
1569 #define BE_PME_D3COLD_CAP 0x80
1634 PHY_TYPE_CX4_10GB = 0,
1651 #define BE_SUPPORTED_SPEED_NONE 0
1656 #define BE_SUPPORTED_SPEED_20GBPS 0x10
1657 #define BE_SUPPORTED_SPEED_40GBPS 0x20
1659 #define BE_AN_EN 0x2
1660 #define BE_PAUSE_SYM_EN 0x80
1663 #define SPEED_DEFAULT 0x0
1664 #define SPEED_FORCED_10GB 0x1
1665 #define SPEED_FORCED_1GB 0x2
1666 #define SPEED_AUTONEG_10GB 0x3
1667 #define SPEED_AUTONEG_1GB 0x4
1668 #define SPEED_AUTONEG_100MB 0x5
1669 #define SPEED_AUTONEG_10GB_1GB 0x6
1670 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1671 #define SPEED_AUTONEG_1GB_100MB 0x8
1672 #define SPEED_AUTONEG_10MB 0x9
1673 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1674 #define SPEED_AUTONEG_100MB_10MB 0xb
1675 #define SPEED_FORCED_100MB 0xc
1676 #define SPEED_FORCED_10MB 0xd
1760 BE_PRIV_DEFAULT = 0x1,
1761 BE_PRIV_LNKQUERY = 0x2,
1762 BE_PRIV_LNKSTATS = 0x4,
1763 BE_PRIV_LNKMGMT = 0x8,
1764 BE_PRIV_LNKDIAG = 0x10,
1765 BE_PRIV_UTILQUERY = 0x20,
1766 BE_PRIV_FILTMGMT = 0x40,
1767 BE_PRIV_IFACEMGMT = 0x80,
1768 BE_PRIV_VHADM = 0x100,
1769 BE_PRIV_DEVCFG = 0x200,
1770 BE_PRIV_DEVSEC = 0x400
1841 #define PORT_FWD_TYPE_VEPA 0x3
1842 #define PORT_FWD_TYPE_VEB 0x2
1843 #define PORT_FWD_TYPE_PASSTHRU 0x1
1845 #define ENABLE_MAC_SPOOFCHK 0x2
1846 #define DISABLE_MAC_SPOOFCHK 0x3
1966 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
2050 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
2075 #define MODE_UART 0
2123 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40
2124 #define NIC_RESOURCE_DESC_TYPE_V0 0x41
2125 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50
2126 #define NIC_RESOURCE_DESC_TYPE_V1 0x51
2127 #define PORT_RESOURCE_DESC_TYPE_V1 0x55
2130 #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */
2151 #define NV_TYPE_MASK 0x3 /* bits 0-1 */
2220 MC_NONE = 0x01,
2221 UMC = 0x02,
2222 FLEX10 = 0x03,
2223 vNIC1 = 0x04,
2224 nPAR = 0x05,
2225 UFP = 0x06,
2226 vNIC2 = 0x07
2253 #define ACTIVE_PROFILE_TYPE 0x2
2254 #define SAVED_PROFILE_TYPE 0x0
2267 #define FIELD_MODIFIABLE 0xFFFF
2321 #define BE_FEATURE_UE_RECOVERY 0x10
2322 #define BE_UE_RECOVERY_UER_MASK 0x1
2356 #define PLINK_ENABLE BIT(0)
2360 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2364 #define OP_CONVERT_NORMAL_TO_TUNNEL 0