143 #define dw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
609 	dw32(DCR0, DM910X_RESET);	/* RESET MAC */  in dmfe_init_dm910x()
611 	dw32(DCR0, db->cr0_data);  in dmfe_init_dm910x()
622 	dw32(DCR12, 0x180);		/* Let bit 7 output port */  in dmfe_init_dm910x()
624 		dw32(DCR12, 0x80);	/* Issue RESET signal */  in dmfe_init_dm910x()
627 	dw32(DCR12, 0x0);	/* Clear RESET signal */  in dmfe_init_dm910x()
651 	dw32(DCR7, db->cr7_data);  in dmfe_init_dm910x()
654 	dw32(DCR15, db->cr15_data);  in dmfe_init_dm910x()
697 	dw32(DCR7, 0);  in dmfe_start_xmit()
711 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
715 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
724 	dw32(DCR7, db->cr7_data);  in dmfe_start_xmit()
752 	dw32(DCR0, DM910X_RESET);  in dmfe_stop()
793 	dw32(DCR5, db->cr5_data);  in dmfe_interrupt()
800 	dw32(DCR7, 0);  in dmfe_interrupt()
832 	dw32(DCR7, db->cr7_data);  in dmfe_interrupt()
917 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_free_tx_pkt()
1164 		dw32(DCR1, 0x1);   /* Tx polling again */  in dmfe_timer()
1285 	dw32(DCR7, 0);				/* Disable Interrupt */  in dmfe_dynamic_reset()
1286 	dw32(DCR5, dr32(DCR5));  in dmfe_dynamic_reset()
1368 	dw32(DCR4, db->first_tx_desc_dma);     /* TX DESC address */  in dmfe_descriptor_init()
1378 	dw32(DCR3, db->first_rx_desc_dma);		/* RX DESC address */  in dmfe_descriptor_init()
1425 	dw32(DCR6, cr6_tmp);  in update_cr6()
1427 	dw32(DCR6, cr6_data);  in update_cr6()
1526 		dw32(DCR1, 0x1);	/* Issue Tx polling */  in send_filter_frame()
1572 		dw32(DCR9, data | cmd[i]);  in srom_clk_write()
1585 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1587 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1601 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1605 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);  in read_srom_word()
1609 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1613 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1871 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1873 	dw32(DCR9, phy_data | MDCLKH);	/* MII Clock High */  in dmfe_phy_write_1bit()
1875 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1888 	dw32(DCR9, 0x50000);  in dmfe_phy_read_1bit()
1891 	dw32(DCR9, 0x40000);  in dmfe_phy_read_1bit()
2102 	dw32(DCR7, 0);  in dmfe_suspend()
2103 	dw32(DCR5, dr32(DCR5));  in dmfe_suspend()