Lines Matching +full:srom +full:- +full:timing
16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
26 #define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */
27 #define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */
28 #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
29 #define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */
30 #define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */
31 #define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/
32 #define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */
33 #define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */
34 #define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */
35 #define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */
36 #define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */
140 #define CFCS_DST 0x06000000 /* DEVSEL Timing (S) */
142 #define CFCS_FBB 0x00800000 /* Fast Back-To-Back (S) */
170 #define CBIO_MASK -128 /* Base I/O Address Mask */
224 /* Timings here are for 10BASE-T/AUI only*/
235 #define CAL_8LONG 0x00004000 /* 8-longword alignment */
236 #define CAL_16LONG 0x00008000 /* 16-longword alignment */
237 #define CAL_32LONG 0x0000c000 /* 32-longword alignment */
288 #define STS_FD 0x00000800 /* Full-Duplex Short Frame Received */
292 #define STS_RWT 0x00000200 /* Receive Watchdog Time-Out */
299 #define STS_TJT 0x00000008 /* Transmit Jabber Time-Out */
335 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
380 #define IMR_FDM 0x00000800 /* Full-Duplex (Short Frame) Mask */
384 #define IMR_RWM 0x00000200 /* Receive Watchdog Time-Out Mask */
391 #define IMR_TJM 0x00000008 /* Transmit Time-Out Jabber Mask */
482 #define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */
483 #define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */
484 #define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */
485 #define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */
486 #define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */
504 #define MII_ANA_CSMA 0x0001 /* CSMA-CD Capable */
519 #define MII_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */
522 ** SROM Media Definitions (ABG SROM Section)
532 ** SROM Definitions (Digital Semiconductor Format)
534 #define SROM_SSVID 0x0000 /* Sub-system Vendor ID offset */
535 #define SROM_SSID 0x0002 /* Sub-system ID offset */
540 #define SROM_SFV 0x0012 /* SROM Format Version offset */
544 #define SROM_CRC 0x007e /* SROM CRC offset */
547 ** SROM Media Connection Definitions
549 #define SROM_10BT 0x0000 /* 10BASE-T half duplex */
550 #define SROM_10BTN 0x0100 /* 10BASE-T with Nway */
551 #define SROM_10BTF 0x0204 /* 10BASE-T full duplex */
552 #define SROM_10BTNLP 0x0400 /* 10BASE-T without Link Pass test */
553 #define SROM_10B2 0x0001 /* 10BASE-2 (BNC) */
554 #define SROM_10B5 0x0002 /* 10BASE-5 (AUI) */
555 #define SROM_100BTH 0x0003 /* 100BASE-T half duplex */
556 #define SROM_100BTF 0x0205 /* 100BASE-T full duplex */
557 #define SROM_100BT4 0x0006 /* 100BASE-T4 */
558 #define SROM_100BFX 0x0007 /* 100BASE-FX half duplex (Fiber) */
559 #define SROM_M10BT 0x0009 /* MII 10BASE-T half duplex */
560 #define SROM_M10BTF 0x020a /* MII 10BASE-T full duplex */
561 #define SROM_M100BT 0x000d /* MII 100BASE-T half duplex */
562 #define SROM_M100BTF 0x020e /* MII 100BASE-T full duplex */
563 #define SROM_M100BT4 0x000f /* MII 100BASE-T4 */
564 #define SROM_M100BF 0x0010 /* MII 100BASE-FX half duplex */
565 #define SROM_M100BFF 0x0211 /* MII 100BASE-FX full duplex */
571 ** SROM Media Definitions
573 #define SROM_10BASET 0x0000 /* 10BASE-T half duplex */
574 #define SROM_10BASE2 0x0001 /* 10BASE-2 (BNC) */
575 #define SROM_10BASE5 0x0002 /* 10BASE-5 (AUI) */
576 #define SROM_100BASET 0x0003 /* 100BASE-T half duplex */
577 #define SROM_10BASETF 0x0004 /* 10BASE-T full duplex */
578 #define SROM_100BASETF 0x0005 /* 100BASE-T full duplex */
579 #define SROM_100BASET4 0x0006 /* 100BASE-T4 */
580 #define SROM_100BASEF 0x0007 /* 100BASE-FX half duplex */
581 #define SROM_100BASEFF 0x0008 /* 100BASE-FX full duplex */
588 ** SROM Compact Format Block Masks
595 ** SROM Extended Format Block Type 0 Masks
644 #define SISR_TRA 0x00000200 /* 10BASE-T Receive Port Activity */
650 #define SISR_DSP 0x00000020 /* PLL Self-Test Pass */
651 #define SISR_DSD 0x00000010 /* PLL Self-Test Done */
665 #define ANS_NWOK 0x00005000 /* Nway OK - FLP Link Good */
680 #define SICR_D_SIA 0x00000400 /* SIA MUX Select Diagnostics - SIA Sigs */
681 #define SICR_DPLL 0x00000800 /* SIA MUX Select Diagnostics - DPLL Sigs*/
682 #define SICR_APLL 0x00000a00 /* SIA MUX Select Diagnostics - DPLL Sigs*/
683 #define SICR_D_RxM 0x00000c00 /* SIA MUX Select Diagnostics - RxM Sigs */
684 #define SICR_M_RxM 0x00000d00 /* SIA MUX Select Diagnostics - RxM Sigs */
685 #define SICR_LNKT 0x00000e00 /* SIA MUX Select Diagnostics - Link Test*/
691 #define SICR_AUI 0x00000008 /* 10Base-T (0) or AUI (1) */
700 #define STRR_TAS 0x00008000 /* 10Base-T/AUI Autosensing Enable */
782 #define TD_TO 0x00004000 /* Transmit Jabber Time-Out */
815 #define TP 0x0040 /* 10Base-T (now equiv to _10Mb) */
816 #define TP_NW 0x0002 /* 10Base-T with Nway */
850 #define DEBUG_SROM 0x0010 /* Print SROM messages */
909 ** IEEE OUIs for various PHY vendor/chip combos - Reg 2 values only. Since
910 ** the vendors seem split 50-50 on how to calculate the OUI register values
922 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
924 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
925 mii_wr(MII_CR_10|(lp->fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
927 omr |= ((lp->fdx ? OMR_FDX : 0) | OMR_TTM);\
929 if (!lp->useSROM) lp->cache.gep = 0;\
930 } else if (lp->useSROM && !lp->useMII) {\
932 omr |= (lp->fdx ? OMR_FDX : 0);\
933 outl(omr | (lp->infoblock_csr6 & ~(OMR_SCR | OMR_HBD)), DE4X5_OMR);\
936 omr |= (lp->fdx ? OMR_FDX : 0);\
938 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD);\
939 gep_wr(lp->cache.gep, dev);\
944 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
946 if (lp->phy[lp->active].id == NATIONAL_TX) {\
947 mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
948 0x18, lp->phy[lp->active].addr, DE4X5_MII);\
951 sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\
952 if (!(sr & MII_ANA_T4AM) && lp->fdx) fdx=1;\
953 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
954 mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
958 if (!lp->useSROM) lp->cache.gep = 0;\
959 } else if (lp->useSROM && !lp->useMII) {\
961 omr |= (lp->fdx ? OMR_FDX : 0);\
962 outl(omr | lp->infoblock_csr6, DE4X5_OMR);\
965 omr |= (lp->fdx ? OMR_FDX : 0);\
967 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD) | GEP_MODE;\
968 gep_wr(lp->cache.gep, dev);\
974 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
975 mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
978 } else if (lp->useSROM && !lp->useMII) {\
984 lp->cache.gep = (GEP_FDXD | GEP_MODE);\
985 gep_wr(lp->cache.gep, dev);\
1017 #define MOTO_SROM_BUG (lp->active == 8 && (get_unaligned_le32(dev->dev_addr) & 0x00ffffff) == 0x…