Lines Matching +full:idma +full:- +full:addr
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
85 * @addr: the register address
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, in t4_set_reg_field() argument
95 u32 v = t4_read_reg(adapter, addr) & ~mask; in t4_set_reg_field()
97 t4_write_reg(adapter, addr, v | val); in t4_set_reg_field()
98 (void) t4_read_reg(adapter, addr); /* flush */ in t4_set_reg_field()
102 * t4_read_indirect - read indirectly addressed registers
117 while (nregs--) { in t4_read_indirect()
125 * t4_write_indirect - write indirectly addressed registers
140 while (nregs--) { in t4_write_indirect()
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); in t4_hw_pci_read_cfg4()
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()
161 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
170 * read-modify-write via t4_set_reg_field().) in t4_hw_pci_read_cfg4()
176 * t4_report_fw_error - report firmware error
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", in t4_report_fw_error()
201 adap->flags &= ~CXGB4_FW_OK; in t4_report_fw_error()
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
211 for ( ; nflit; nflit--, mbox_addr += 8) in get_mbox_rpl()
223 dev_alert(adap->pdev_dev, in fw_asrt()
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
241 struct mbox_cmd_log *log = adapter->mbox_log; in t4_record_mbox()
245 entry = mbox_cmd_log_entry(log, log->cursor++); in t4_record_mbox()
246 if (log->cursor == log->size) in t4_record_mbox()
247 log->cursor = 0; in t4_record_mbox()
250 entry->cmd[i] = be64_to_cpu(cmd[i]); in t4_record_mbox()
252 entry->cmd[i++] = 0; in t4_record_mbox()
253 entry->timestamp = jiffies; in t4_record_mbox()
254 entry->seqno = log->seqno++; in t4_record_mbox()
255 entry->access = access; in t4_record_mbox()
256 entry->execute = execute; in t4_record_mbox()
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
302 return -EINVAL; in t4_wr_mbox_meat_timeout()
305 * If the device is off-line, as in EEH, commands will time out. in t4_wr_mbox_meat_timeout()
308 if (adap->pdev->error_state != pci_channel_io_normal) in t4_wr_mbox_meat_timeout()
309 return -EIO; in t4_wr_mbox_meat_timeout()
314 timeout = -timeout; in t4_wr_mbox_meat_timeout()
322 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
323 list_add_tail(&entry.list, &adap->mlist.list); in t4_wr_mbox_meat_timeout()
324 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
337 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
339 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY; in t4_wr_mbox_meat_timeout()
348 if (list_first_entry(&adap->mlist.list, struct mbox_list, in t4_wr_mbox_meat_timeout()
355 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
370 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
372 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
395 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
423 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
425 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
426 return -FW_CMD_RETVAL_G((int)res); in t4_wr_mbox_meat_timeout()
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", in t4_wr_mbox_meat_timeout()
435 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
437 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
454 if (is_t4(adap->params.chip)) { in t4_edc_err_read()
467 "edc%d err addr 0x%x: 0x%x.\n", in t4_edc_err_read()
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller in t4_memory_rw_init()
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) in t4_memory_rw_init()
520 /* Each PCI-E Memory Window is programmed with a window size -- or in t4_memory_rw_init()
521 * "aperture" -- which controls the granularity of its mapping onto in t4_memory_rw_init()
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5 in t4_memory_rw_init()
533 return -ENXIO; in t4_memory_rw_init()
537 if (is_t4(adap->params.chip)) in t4_memory_rw_init()
538 *mem_base -= adap->t4_bar0; in t4_memory_rw_init()
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr) in t4_memory_update_win() argument
555 addr); in t4_memory_update_win()
564 * t4_memory_rw_residual - Read/Write residual data.
567 * @addr: address within indicated memory type.
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, in t4_memory_rw_residual() argument
585 t4_read_reg(adap, addr)); in t4_memory_rw_residual()
592 t4_write_reg(adap, addr, in t4_memory_rw_residual()
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
602 * @addr: address within indicated memory type
608 * firmware memory address and host buffer must be aligned on 32-bit
611 * contains data structures which contain multi-byte integers, it's the
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, in t4_memory_rw() argument
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3) in t4_memory_rw()
625 return -EINVAL; in t4_memory_rw()
629 * multiple of 32-bits because we often end up transferring files to in t4_memory_rw()
634 len -= resid; in t4_memory_rw()
642 addr = addr + memoffset; in t4_memory_rw()
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); in t4_memory_rw()
646 /* Calculate our initial PCI-E Memory Window Position and Offset into in t4_memory_rw()
649 pos = addr & ~(mem_aperture - 1); in t4_memory_rw()
650 offset = addr - pos; in t4_memory_rw()
652 /* Set up initial PCI-E Memory Window to cover the start of our in t4_memory_rw()
658 * number of 32-bit transfers to complete. in t4_memory_rw()
662 * The "register" reads and writes below from/to the PCI-E Memory in t4_memory_rw()
663 * Window invoke the standard adapter Big-Endian to PCI-E Link in t4_memory_rw()
664 * Little-Endian "swizzel." As a result, if we have the following in t4_memory_rw()
670 * Then a read of the adapter memory via the PCI-E Memory Window in t4_memory_rw()
677 * If this value is stored into local memory on a Little-Endian system in t4_memory_rw()
682 * But on a Big-Endian system, the store will show up in memory in t4_memory_rw()
688 * PCI-E Memory Window below by undoing the register read/write in t4_memory_rw()
699 len -= sizeof(__be32); in t4_memory_rw()
702 * move the PCI-E Memory Window on to the next. Note that in t4_memory_rw()
704 * the PCI-E Memory Window for a possible final residual in t4_memory_rw()
715 * 32-bits, now's where we need to finish off the transfer of the in t4_memory_rw()
716 * residual amount. The PCI-E Memory Window has already been moved in t4_memory_rw()
726 /* Return the specified PCI-E Configuration Space register from our Physical
736 * retrieve the specified PCI-E Configuration Space register. in t4_read_pcie_cfg4()
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); in t4_read_pcie_cfg4()
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
761 /* Read the desired Configuration Space register via the PCI-E in t4_read_pcie_cfg4()
777 if (is_t4(adap->params.chip)) { in t4_get_window()
780 /* Truncation intentional: we only read the bottom 32-bits of in t4_get_window()
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor in t4_get_window()
785 * our Configuration Space and we need to set up the PCI-E in t4_get_window()
787 * be coming across the PCI-E link. in t4_get_window()
791 adap->t4_bar0 = bar0; in t4_get_window()
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X)); in t4_setup_memwin()
823 * t4_get_regs_len - return the size of the chips register set
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_get_regs_len()
841 dev_err(adapter->pdev_dev, in t4_get_regs_len()
847 * t4_get_regs - read chip registers into provided buffer
2642 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2664 dev_err(adap->pdev_dev, in t4_get_regs()
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2698 * @sz: size of function-specific area
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2717 return 31744 - fn + phys_addr - 1024; in t4_eeprom_ptov()
2719 return phys_addr - 1024 - fn; in t4_eeprom_ptov()
2720 return -EINVAL; in t4_eeprom_ptov()
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2733 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); in t4_seeprom_wp()
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2746 int i, ret = 0, addr; in t4_get_raw_vpd_params() local
2753 return -ENOMEM; in t4_get_raw_vpd_params()
2758 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd); in t4_get_raw_vpd_params()
2768 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; in t4_get_raw_vpd_params()
2770 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); in t4_get_raw_vpd_params()
2775 dev_err(adapter->pdev_dev, "missing VPD ID string\n"); in t4_get_raw_vpd_params()
2776 ret = -EINVAL; in t4_get_raw_vpd_params()
2786 dev_err(adapter->pdev_dev, "missing VPD-R section\n"); in t4_get_raw_vpd_params()
2787 ret = -EINVAL; in t4_get_raw_vpd_params()
2794 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); in t4_get_raw_vpd_params()
2795 ret = -EINVAL; in t4_get_raw_vpd_params()
2802 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ in t4_get_raw_vpd_params()
2803 ret = -EINVAL; \ in t4_get_raw_vpd_params()
2810 for (csum = 0; i >= 0; i--) in t4_get_raw_vpd_params()
2814 dev_err(adapter->pdev_dev, in t4_get_raw_vpd_params()
2816 ret = -EINVAL; in t4_get_raw_vpd_params()
2826 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); in t4_get_raw_vpd_params()
2827 strim(p->id); in t4_get_raw_vpd_params()
2828 memcpy(p->ec, vpd + ec, EC_LEN); in t4_get_raw_vpd_params()
2829 strim(p->ec); in t4_get_raw_vpd_params()
2830 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); in t4_get_raw_vpd_params()
2831 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); in t4_get_raw_vpd_params()
2832 strim(p->sn); in t4_get_raw_vpd_params()
2833 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE); in t4_get_raw_vpd_params()
2834 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); in t4_get_raw_vpd_params()
2835 strim(p->pn); in t4_get_raw_vpd_params()
2836 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); in t4_get_raw_vpd_params()
2837 strim((char *)p->na); in t4_get_raw_vpd_params()
2845 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2869 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_params()
2874 p->cclk = cclk_val; in t4_get_vpd_params()
2880 * t4_get_pfres - retrieve VF resource limits
2884 * function. The results are stored in @adapter->pfres.
2888 struct pf_resources *pfres = &adapter->params.pfres; in t4_get_pfres()
2900 FW_PFVF_CMD_PFN_V(adapter->pf) | in t4_get_pfres()
2903 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl); in t4_get_pfres()
2910 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word); in t4_get_pfres()
2911 pfres->niq = FW_PFVF_CMD_NIQ_G(word); in t4_get_pfres()
2914 pfres->neq = FW_PFVF_CMD_NEQ_G(word); in t4_get_pfres()
2915 pfres->pmask = FW_PFVF_CMD_PMASK_G(word); in t4_get_pfres()
2918 pfres->tc = FW_PFVF_CMD_TC_G(word); in t4_get_pfres()
2919 pfres->nvi = FW_PFVF_CMD_NVI_G(word); in t4_get_pfres()
2920 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word); in t4_get_pfres()
2923 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word); in t4_get_pfres()
2924 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word); in t4_get_pfres()
2925 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word); in t4_get_pfres()
2945 * sf1_read - read data from the serial flash
2962 return -EINVAL; in sf1_read()
2964 return -EBUSY; in sf1_read()
2966 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); in sf1_read()
2974 * sf1_write - write data to the serial flash
2989 return -EINVAL; in sf1_write()
2991 return -EBUSY; in sf1_write()
2994 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); in sf1_write()
2999 * flash_wait_op - wait for a flash operation to complete
3017 if (--attempts == 0) in flash_wait_op()
3018 return -EAGAIN; in flash_wait_op()
3025 * t4_read_flash - read words from serial flash
3027 * @addr: the start address for the read
3028 * @nwords: how many 32-bit words to read
3032 * Read the specified number of 32-bit words from the serial flash.
3034 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3037 int t4_read_flash(struct adapter *adapter, unsigned int addr, in t4_read_flash() argument
3042 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
3043 return -EINVAL; in t4_read_flash()
3045 addr = swab32(addr) | SF_RD_DATA_FAST; in t4_read_flash()
3047 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || in t4_read_flash()
3051 for ( ; nwords; nwords--, data++) { in t4_read_flash()
3064 * t4_write_flash - write up to a page of data to the serial flash
3066 * @addr: the start address to write
3073 static int t4_write_flash(struct adapter *adapter, unsigned int addr, in t4_write_flash() argument
3078 unsigned int i, c, left, val, offset = addr & 0xff; in t4_write_flash()
3080 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
3081 return -EINVAL; in t4_write_flash()
3083 val = swab32(addr) | SF_PROG_PAGE; in t4_write_flash()
3089 for (left = n; left; left -= c) { in t4_write_flash()
3105 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); in t4_write_flash()
3109 if (memcmp(data - n, (u8 *)buf + offset, n)) { in t4_write_flash()
3110 dev_err(adapter->pdev_dev, in t4_write_flash()
3112 addr); in t4_write_flash()
3113 return -EIO; in t4_write_flash()
3123 * t4_get_fw_version - read the firmware version
3137 * t4_get_bs_version - read the firmware bootstrap version
3151 * t4_get_tp_version - read the TP microcode version
3165 * t4_get_exprom_version - return the Expansion ROM version (if any)
3172 * 0 on success, -ENOENT if no Expansion ROM is present.
3191 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) in t4_get_exprom_version()
3192 return -ENOENT; in t4_get_exprom_version()
3194 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) | in t4_get_exprom_version()
3195 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) | in t4_get_exprom_version()
3196 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) | in t4_get_exprom_version()
3197 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3])); in t4_get_exprom_version()
3202 * t4_get_vpd_version - return the VPD version
3212 * to retrieve the VPD version, so we zero-out the return-value parameter
3229 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_version()
3237 * t4_get_scfg_version - return the Serial Configuration version
3247 * to retrieve the Serial Configuration version, so we zero-out the
3248 * return-value parameter in that case to avoid leaving it with
3266 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_scfg_version()
3274 * t4_get_version_info - extract various chip/firmware version information
3293 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); in t4_get_version_info()
3294 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); in t4_get_version_info()
3295 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); in t4_get_version_info()
3296 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); in t4_get_version_info()
3297 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); in t4_get_version_info()
3298 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); in t4_get_version_info()
3305 * t4_dump_version_info - dump all of the adapter configuration IDs
3315 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n", in t4_dump_version_info()
3316 adapter->params.vpd.id, in t4_dump_version_info()
3317 CHELSIO_CHIP_RELEASE(adapter->params.chip)); in t4_dump_version_info()
3318 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n", in t4_dump_version_info()
3319 adapter->params.vpd.sn, adapter->params.vpd.pn); in t4_dump_version_info()
3322 if (!adapter->params.fw_vers) in t4_dump_version_info()
3323 dev_warn(adapter->pdev_dev, "No firmware loaded\n"); in t4_dump_version_info()
3325 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n", in t4_dump_version_info()
3326 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers), in t4_dump_version_info()
3327 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers), in t4_dump_version_info()
3328 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers), in t4_dump_version_info()
3329 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers)); in t4_dump_version_info()
3334 if (!adapter->params.bs_vers) in t4_dump_version_info()
3335 dev_info(adapter->pdev_dev, "No bootstrap loaded\n"); in t4_dump_version_info()
3337 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n", in t4_dump_version_info()
3338 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers), in t4_dump_version_info()
3339 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers), in t4_dump_version_info()
3340 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers), in t4_dump_version_info()
3341 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers)); in t4_dump_version_info()
3344 if (!adapter->params.tp_vers) in t4_dump_version_info()
3345 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n"); in t4_dump_version_info()
3347 dev_info(adapter->pdev_dev, in t4_dump_version_info()
3349 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers), in t4_dump_version_info()
3350 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers), in t4_dump_version_info()
3351 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers), in t4_dump_version_info()
3352 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers)); in t4_dump_version_info()
3355 if (!adapter->params.er_vers) in t4_dump_version_info()
3356 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n"); in t4_dump_version_info()
3358 dev_info(adapter->pdev_dev, in t4_dump_version_info()
3360 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers), in t4_dump_version_info()
3361 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers), in t4_dump_version_info()
3362 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers), in t4_dump_version_info()
3363 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers)); in t4_dump_version_info()
3366 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n", in t4_dump_version_info()
3367 adapter->params.scfg_vers); in t4_dump_version_info()
3370 dev_info(adapter->pdev_dev, "VPD version: %#x\n", in t4_dump_version_info()
3371 adapter->params.vpd_vers); in t4_dump_version_info()
3375 * t4_check_fw_version - check if the FW is supported with this driver
3386 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_check_fw_version()
3388 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3390 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++) in t4_check_fw_version()
3391 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3396 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); in t4_check_fw_version()
3397 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); in t4_check_fw_version()
3398 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); in t4_check_fw_version()
3417 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", in t4_check_fw_version()
3418 adap->chip); in t4_check_fw_version()
3419 return -EINVAL; in t4_check_fw_version()
3424 dev_err(adap->pdev_dev, in t4_check_fw_version()
3428 return -EFAULT; in t4_check_fw_version()
3440 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) in fw_compatible()
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) in fw_compatible()
3444 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && in fw_compatible()
3474 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " in should_install_fs_fw()
3493 drv_fw = &fw_info->fw_hdr; in t4_prep_fw()
3502 dev_err(adap->pdev_dev, in t4_prep_fw()
3515 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && in t4_prep_fw()
3516 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { in t4_prep_fw()
3523 be32_to_cpu(fs_fw->fw_ver), in t4_prep_fw()
3524 be32_to_cpu(card_fw->fw_ver))) { in t4_prep_fw()
3525 ret = t4_fw_upgrade(adap, adap->mbox, fw_data, in t4_prep_fw()
3528 dev_err(adap->pdev_dev, in t4_prep_fw()
3542 d = be32_to_cpu(drv_fw->fw_ver); in t4_prep_fw()
3543 c = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3544 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; in t4_prep_fw()
3546 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " in t4_prep_fw()
3557 ret = -EINVAL; in t4_prep_fw()
3562 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3563 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
3570 * t4_flash_erase_sectors - erase a range of flash sectors
3581 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
3582 return -EINVAL; in t4_flash_erase_sectors()
3589 dev_err(adapter->pdev_dev, in t4_flash_erase_sectors()
3601 * t4_flash_cfg_addr - return the address of the flash configuration file
3609 if (adapter->params.sf_size == 0x100000) in t4_flash_cfg_addr()
3626 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3627 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3628 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3631 dev_err(adap->pdev_dev, in t4_fw_matches_chip()
3633 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
3638 * t4_load_fw - download firmware
3648 int ret, addr; in t4_load_fw() local
3653 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3659 dev_err(adap->pdev_dev, "FW image has no data\n"); in t4_load_fw()
3660 return -EINVAL; in t4_load_fw()
3663 dev_err(adap->pdev_dev, in t4_load_fw()
3665 return -EINVAL; in t4_load_fw()
3667 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) { in t4_load_fw()
3668 dev_err(adap->pdev_dev, in t4_load_fw()
3670 return -EINVAL; in t4_load_fw()
3673 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", in t4_load_fw()
3675 return -EFBIG; in t4_load_fw()
3678 return -EINVAL; in t4_load_fw()
3684 dev_err(adap->pdev_dev, in t4_load_fw()
3686 return -EINVAL; in t4_load_fw()
3690 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
3700 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); in t4_load_fw()
3705 addr = fw_start; in t4_load_fw()
3706 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_fw()
3707 addr += SF_PAGE_SIZE; in t4_load_fw()
3709 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); in t4_load_fw()
3716 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); in t4_load_fw()
3719 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", in t4_load_fw()
3722 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
3727 * t4_phy_fw_ver - return current PHY firmware version
3741 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_phy_fw_ver()
3743 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_phy_fw_ver()
3752 * t4_load_phy_fw - download port PHY firmware
3754 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3759 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3785 * already has up-to-date PHY firmware loaded. in t4_load_phy_fw()
3794 CH_WARN(adap, "PHY Firmware already up-to-date, " in t4_load_phy_fw()
3808 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3811 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3834 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3836 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3852 return -ENXIO; in t4_load_phy_fw()
3860 * t4_fwcache - firmware cache operation
3872 FW_PARAMS_CMD_PFN_V(adap->pf) | in t4_fwcache()
3880 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
3954 * Capabilities which we control with separate controls -- see, for instance,
3965 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3966 * @caps16: a 16-bit Port Capabilities value
3968 * Returns the equivalent 32-bit Port Capabilities value.
4003 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4004 * @caps32: a 32-bit Port Capabilities value
4006 * Returns the equivalent 16-bit Port Capabilities value. Note that
4007 * not all 32-bit Port Capabilities can be represented in the 16-bit
4114 * t4_link_acaps - compute Link Advertised Port Capabilities
4131 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps); in t4_link_acaps()
4136 fw_fc = cc_to_fwcap_pause(lc->requested_fc); in t4_link_acaps()
4141 * sent us as part of its IEEE 802.3-based interpretation of in t4_link_acaps()
4145 if (lc->requested_fec & FEC_AUTO) in t4_link_acaps()
4146 cc_fec = fwcap_to_cc_fec(lc->def_acaps); in t4_link_acaps()
4148 cc_fec = lc->requested_fec; in t4_link_acaps()
4155 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { in t4_link_acaps()
4156 acaps = lc->acaps | fw_fc | fw_fec; in t4_link_acaps()
4157 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in t4_link_acaps()
4158 lc->fec = cc_fec; in t4_link_acaps()
4159 } else if (lc->autoneg == AUTONEG_DISABLE) { in t4_link_acaps()
4160 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi; in t4_link_acaps()
4161 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in t4_link_acaps()
4162 lc->fec = cc_fec; in t4_link_acaps()
4164 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi; in t4_link_acaps()
4175 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) { in t4_link_acaps()
4176 …dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\… in t4_link_acaps()
4177 acaps, lc->pcaps); in t4_link_acaps()
4178 return -EINVAL; in t4_link_acaps()
4185 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4195 * - If the PHY can auto-negotiate first decide what to advertise, then
4196 * enable/disable auto-negotiation as desired, and reset.
4197 * - If the PHY does not auto-negotiate just reset it.
4198 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4199 * otherwise do it later based on the outcome of auto-negotiation.
4205 unsigned int fw_caps = adapter->params.fw_caps_support; in t4_link_l1cfg_core()
4210 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) && in t4_link_l1cfg_core()
4211 lc->autoneg == AUTONEG_ENABLE) { in t4_link_l1cfg_core()
4212 return -EINVAL; in t4_link_l1cfg_core()
4238 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward in t4_link_l1cfg_core()
4243 dev_err(adapter->pdev_dev, in t4_link_l1cfg_core()
4245 rcap, -ret); in t4_link_l1cfg_core()
4252 * t4_restart_aneg - restart autonegotiation
4261 unsigned int fw_caps = adap->params.fw_caps_support; in t4_restart_aneg()
4285 short stat_idx; /* stat counter to increment or -1 */
4287 int_handler_t int_handler; /* platform-specific int handler */
4291 * t4_handle_intr_status - table driven interrupt handler
4310 for ( ; acts->mask; ++acts) { in t4_handle_intr_status()
4311 if (!(status & acts->mask)) in t4_handle_intr_status()
4313 if (acts->fatal) { in t4_handle_intr_status()
4315 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, in t4_handle_intr_status()
4316 status & acts->mask); in t4_handle_intr_status()
4317 } else if (acts->msg && printk_ratelimit()) in t4_handle_intr_status()
4318 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, in t4_handle_intr_status()
4319 status & acts->mask); in t4_handle_intr_status()
4320 if (acts->int_handler) in t4_handle_intr_status()
4321 acts->int_handler(adapter); in t4_handle_intr_status()
4322 mask |= acts->mask; in t4_handle_intr_status()
4336 { RNPP_F, "RXNP array parity error", -1, 1 }, in pcie_intr_handler()
4337 { RPCP_F, "RXPC array parity error", -1, 1 }, in pcie_intr_handler()
4338 { RCIP_F, "RXCIF array parity error", -1, 1 }, in pcie_intr_handler()
4339 { RCCP_F, "Rx completions control array parity error", -1, 1 }, in pcie_intr_handler()
4340 { RFTP_F, "RXFT array parity error", -1, 1 }, in pcie_intr_handler()
4344 { TPCP_F, "TXPC array parity error", -1, 1 }, in pcie_intr_handler()
4345 { TNPP_F, "TXNP array parity error", -1, 1 }, in pcie_intr_handler()
4346 { TFTP_F, "TXFT array parity error", -1, 1 }, in pcie_intr_handler()
4347 { TCAP_F, "TXCA array parity error", -1, 1 }, in pcie_intr_handler()
4348 { TCIP_F, "TXCIF array parity error", -1, 1 }, in pcie_intr_handler()
4349 { RCAP_F, "RXCA array parity error", -1, 1 }, in pcie_intr_handler()
4350 { OTDD_F, "outbound request TLP discarded", -1, 1 }, in pcie_intr_handler()
4351 { RDPE_F, "Rx data parity error", -1, 1 }, in pcie_intr_handler()
4352 { TDUE_F, "Tx uncorrectable data error", -1, 1 }, in pcie_intr_handler()
4356 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, in pcie_intr_handler()
4357 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, in pcie_intr_handler()
4358 { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, in pcie_intr_handler()
4359 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, in pcie_intr_handler()
4360 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, in pcie_intr_handler()
4361 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, in pcie_intr_handler()
4362 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, in pcie_intr_handler()
4363 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, in pcie_intr_handler()
4364 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, in pcie_intr_handler()
4365 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, in pcie_intr_handler()
4366 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, in pcie_intr_handler()
4367 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, in pcie_intr_handler()
4368 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, in pcie_intr_handler()
4369 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4370 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4371 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4372 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4373 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4374 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4375 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, in pcie_intr_handler()
4376 { FIDPERR_F, "PCI FID parity error", -1, 1 }, in pcie_intr_handler()
4377 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, in pcie_intr_handler()
4378 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, in pcie_intr_handler()
4379 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, in pcie_intr_handler()
4380 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, in pcie_intr_handler()
4381 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, in pcie_intr_handler()
4382 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, in pcie_intr_handler()
4383 { PCIESINT_F, "PCI core secondary fault", -1, 1 }, in pcie_intr_handler()
4384 { PCIEPINT_F, "PCI core primary fault", -1, 1 }, in pcie_intr_handler()
4386 -1, 0 }, in pcie_intr_handler()
4392 -1, 1 }, in pcie_intr_handler()
4393 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in pcie_intr_handler()
4394 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, in pcie_intr_handler()
4395 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, in pcie_intr_handler()
4396 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, in pcie_intr_handler()
4397 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, in pcie_intr_handler()
4398 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, in pcie_intr_handler()
4400 -1, 1 }, in pcie_intr_handler()
4402 -1, 1 }, in pcie_intr_handler()
4403 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, in pcie_intr_handler()
4404 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, in pcie_intr_handler()
4405 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, in pcie_intr_handler()
4406 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, in pcie_intr_handler()
4408 -1, 1 }, in pcie_intr_handler()
4409 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4410 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4411 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4412 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4413 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4414 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, in pcie_intr_handler()
4415 { FIDPERR_F, "PCI FID parity error", -1, 1 }, in pcie_intr_handler()
4416 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, in pcie_intr_handler()
4417 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, in pcie_intr_handler()
4418 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, in pcie_intr_handler()
4420 -1, 1 }, in pcie_intr_handler()
4422 -1, 1 }, in pcie_intr_handler()
4423 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, in pcie_intr_handler()
4424 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, in pcie_intr_handler()
4425 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, in pcie_intr_handler()
4426 { READRSPERR_F, "Outbound read error", -1, 0 }, in pcie_intr_handler()
4432 if (is_t4(adapter->params.chip)) in pcie_intr_handler()
4455 { 0x3fffffff, "TP parity error", -1, 1 }, in tp_intr_handler()
4456 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, in tp_intr_handler()
4474 "SGE received CPL exceeding IQE size", -1, 1 }, in sge_intr_handler()
4476 "SGE GTS CIDX increment too large", -1, 0 }, in sge_intr_handler()
4477 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, in sge_intr_handler()
4478 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, in sge_intr_handler()
4480 "SGE IQID > 1023 received CPL for FL", -1, 0 }, in sge_intr_handler()
4481 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, in sge_intr_handler()
4483 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, in sge_intr_handler()
4485 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, in sge_intr_handler()
4487 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, in sge_intr_handler()
4490 "SGE too many priority ingress contexts", -1, 0 }, in sge_intr_handler()
4491 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, in sge_intr_handler()
4492 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, in sge_intr_handler()
4497 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, in sge_intr_handler()
4498 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, in sge_intr_handler()
4500 "SGE too many priority egress contexts", -1, 0 }, in sge_intr_handler()
4507 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n", in sge_intr_handler()
4514 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n", in sge_intr_handler()
4518 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) { in sge_intr_handler()
4524 dev_alert(adapter->pdev_dev, in sge_intr_handler()
4530 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in sge_intr_handler()
4536 dev_err(adapter->pdev_dev, "SGE error for queue %u\n", in sge_intr_handler()
4539 dev_err(adapter->pdev_dev, in sge_intr_handler()
4560 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, in cim_intr_handler()
4561 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, in cim_intr_handler()
4562 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, in cim_intr_handler()
4563 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, in cim_intr_handler()
4564 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, in cim_intr_handler()
4565 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, in cim_intr_handler()
4566 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, in cim_intr_handler()
4567 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 }, in cim_intr_handler()
4571 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, in cim_intr_handler()
4572 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, in cim_intr_handler()
4573 { ILLWRINT_F, "CIM illegal write", -1, 1 }, in cim_intr_handler()
4574 { ILLRDINT_F, "CIM illegal read", -1, 1 }, in cim_intr_handler()
4575 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, in cim_intr_handler()
4576 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, in cim_intr_handler()
4577 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, in cim_intr_handler()
4578 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, in cim_intr_handler()
4579 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, in cim_intr_handler()
4580 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, in cim_intr_handler()
4581 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, in cim_intr_handler()
4582 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, in cim_intr_handler()
4583 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, in cim_intr_handler()
4584 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, in cim_intr_handler()
4585 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, in cim_intr_handler()
4586 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, in cim_intr_handler()
4587 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, in cim_intr_handler()
4588 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, in cim_intr_handler()
4589 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, in cim_intr_handler()
4590 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, in cim_intr_handler()
4591 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, in cim_intr_handler()
4592 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, in cim_intr_handler()
4593 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, in cim_intr_handler()
4594 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, in cim_intr_handler()
4595 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, in cim_intr_handler()
4596 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, in cim_intr_handler()
4597 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, in cim_intr_handler()
4598 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, in cim_intr_handler()
4637 { 0x1800000, "ULPRX context error", -1, 1 }, in ulprx_intr_handler()
4638 { 0x7fffff, "ULPRX parity error", -1, 1 }, in ulprx_intr_handler()
4652 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, in ulptx_intr_handler()
4654 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, in ulptx_intr_handler()
4656 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, in ulptx_intr_handler()
4658 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, in ulptx_intr_handler()
4660 { 0xfffffff, "ULPTX parity error", -1, 1 }, in ulptx_intr_handler()
4674 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4675 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4676 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4677 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, in pmtx_intr_handler()
4678 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, in pmtx_intr_handler()
4679 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, in pmtx_intr_handler()
4681 -1, 1 }, in pmtx_intr_handler()
4682 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, in pmtx_intr_handler()
4683 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, in pmtx_intr_handler()
4697 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, in pmrx_intr_handler()
4698 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, in pmrx_intr_handler()
4699 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, in pmrx_intr_handler()
4701 -1, 1 }, in pmrx_intr_handler()
4702 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, in pmrx_intr_handler()
4703 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, in pmrx_intr_handler()
4717 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, in cplsw_intr_handler()
4718 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, in cplsw_intr_handler()
4719 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, in cplsw_intr_handler()
4720 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, in cplsw_intr_handler()
4721 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, in cplsw_intr_handler()
4722 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, in cplsw_intr_handler()
4735 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); in le_intr_handler()
4737 { LIPMISS_F, "LE LIP miss", -1, 0 }, in le_intr_handler()
4738 { LIP0_F, "LE 0 LIP error", -1, 0 }, in le_intr_handler()
4739 { PARITYERR_F, "LE parity error", -1, 1 }, in le_intr_handler()
4740 { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in le_intr_handler()
4741 { REQQPARERR_F, "LE request queue parity error", -1, 1 }, in le_intr_handler()
4746 { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, in le_intr_handler()
4747 { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, in le_intr_handler()
4748 { CMDTIDERR_F, "LE cmd tid error", -1, 1 }, in le_intr_handler()
4749 { TCAMINTPERR_F, "LE parity error", -1, 1 }, in le_intr_handler()
4750 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in le_intr_handler()
4751 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, in le_intr_handler()
4752 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 }, in le_intr_handler()
4768 { 0xffffff, "MPS Rx parity error", -1, 1 }, in mps_intr_handler()
4772 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, in mps_intr_handler()
4773 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, in mps_intr_handler()
4775 -1, 1 }, in mps_intr_handler()
4777 -1, 1 }, in mps_intr_handler()
4778 { BUBBLE_F, "MPS Tx underflow", -1, 1 }, in mps_intr_handler()
4779 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, in mps_intr_handler()
4780 { FRMERR_F, "MPS Tx framing error", -1, 1 }, in mps_intr_handler()
4784 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, in mps_intr_handler()
4785 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, in mps_intr_handler()
4787 -1, 1 }, in mps_intr_handler()
4789 -1, 1 }, in mps_intr_handler()
4791 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, in mps_intr_handler()
4792 { FRMERR_F, "MPS Tx framing error", -1, 1 }, in mps_intr_handler()
4796 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, in mps_intr_handler()
4798 -1, 1 }, in mps_intr_handler()
4799 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, in mps_intr_handler()
4803 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, in mps_intr_handler()
4807 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, in mps_intr_handler()
4811 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, in mps_intr_handler()
4815 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, in mps_intr_handler()
4816 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, in mps_intr_handler()
4817 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, in mps_intr_handler()
4826 is_t6(adapter->params.chip) in mps_intr_handler()
4856 unsigned int addr, cnt_addr, v; in mem_intr_handler() local
4859 addr = EDC_REG(EDC_INT_CAUSE_A, idx); in mem_intr_handler()
4862 if (is_t4(adapter->params.chip)) { in mem_intr_handler()
4863 addr = MC_INT_CAUSE_A; in mem_intr_handler()
4866 addr = MC_P_INT_CAUSE_A; in mem_intr_handler()
4870 addr = MC_REG(MC_P_INT_CAUSE_A, 1); in mem_intr_handler()
4874 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; in mem_intr_handler()
4876 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", in mem_intr_handler()
4885 dev_warn(adapter->pdev_dev, in mem_intr_handler()
4890 dev_alert(adapter->pdev_dev, in mem_intr_handler()
4893 t4_write_reg(adapter, addr, v); in mem_intr_handler()
4906 dev_alert(adap->pdev_dev, in ma_intr_handler()
4909 if (is_t5(adap->params.chip)) in ma_intr_handler()
4910 dev_alert(adap->pdev_dev, in ma_intr_handler()
4917 dev_alert(adap->pdev_dev, "MA address wrap-around error by " in ma_intr_handler()
4932 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, in smb_intr_handler()
4933 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, in smb_intr_handler()
4934 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, in smb_intr_handler()
4943 * NC-SI interrupt handler.
4948 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, in ncsi_intr_handler()
4949 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, in ncsi_intr_handler()
4950 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, in ncsi_intr_handler()
4951 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, in ncsi_intr_handler()
4966 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
4978 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", in xgmac_intr_handler()
4981 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", in xgmac_intr_handler()
4993 { FATALPERR_F, "T4 fatal parity error", -1, 1 }, in pl_intr_handler()
4994 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, in pl_intr_handler()
5008 * t4_slow_intr_handler - control path interrupt handler
5011 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5049 if (is_t5(adapter->params.chip) && (cause & MC1_F)) in t4_slow_intr_handler()
5081 * t4_intr_enable - enable interrupts
5084 * Enable PF-specific interrupts for the calling function and the top-level
5090 * non PF-specific interrupts from the various HW modules. Only one PCI
5097 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_enable()
5100 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4_intr_enable()
5114 * t4_intr_disable - disable interrupts
5117 * Disable interrupts. We only disable the top-level interrupt
5125 if (pci_channel_offline(adapter->pdev)) in t4_intr_disable()
5129 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_disable()
5138 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_chip_rss_size()
5145 * t4_config_rss_range - configure a portion of the RSS mapping table
5184 n -= nq; in t4_config_rss_range()
5200 nq -= 3; in t4_config_rss_range()
5211 * t4_config_glbl_rss - configure the global RSS mode
5215 * @flags: mode-specific flags
5236 return -EINVAL; in t4_config_glbl_rss()
5241 * t4_config_vi_rss - configure per VI RSS settings
5248 * Configures VI-specific RSS properties.
5274 * t4_read_rss - read the contents of the RSS mapping table
5278 * Reads the contents of the RSS hash->queue mapping table.
5298 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd; in t4_use_ldst()
5302 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5330 c.u.addrval.addr = cpu_to_be32(start_index + i); in t4_tp_fw_ldst_rw()
5332 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, in t4_tp_fw_ldst_rw()
5344 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5361 int rc = -EINVAL; in t4_tp_indirect_rw()
5395 * t4_tp_pio_read - Read TP PIO registers
5412 * t4_tp_pio_write - Write TP PIO registers
5429 * t4_tp_tm_pio_read - Read TP TM PIO registers
5446 * t4_tp_mib_read - Read TP MIB registers
5463 * t4_read_rss_key - read the global RSS key
5465 * @key: 10-entry array holding the 320-bit RSS key
5468 * Reads the global 320-bit RSS key.
5476 * t4_write_rss_key - program one of the RSS keys
5478 * @key: 10-entry array holding the 320-bit RSS key
5482 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5492 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble), in t4_write_rss_key()
5493 * allows access to key addresses 16-63 by using KeyWrAddrX in t4_write_rss_key()
5496 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
5514 * t4_read_rss_pf_config - read PF RSS Configuration Table
5530 * t4_read_rss_vf_config - read VF RSS Configuration Table
5545 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { in t4_read_rss_vf_config()
5567 * t4_read_rss_pf_map - read PF RSS Map
5582 * t4_read_rss_pf_mask - read PF RSS Mask
5597 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5609 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; in t4_tp_get_tcp_stats()
5611 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) in t4_tp_get_tcp_stats()
5618 v4->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
5619 v4->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
5620 v4->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
5621 v4->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
5626 v6->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
5627 v6->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
5628 v6->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
5629 v6->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
5637 * t4_tp_get_err_stats - read TP's error MIB counters
5647 int nchan = adap->params.arch.nchan; in t4_tp_get_err_stats()
5649 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A, in t4_tp_get_err_stats()
5651 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A, in t4_tp_get_err_stats()
5653 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A, in t4_tp_get_err_stats()
5655 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, in t4_tp_get_err_stats()
5657 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, in t4_tp_get_err_stats()
5659 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A, in t4_tp_get_err_stats()
5661 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, in t4_tp_get_err_stats()
5663 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, in t4_tp_get_err_stats()
5665 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A, in t4_tp_get_err_stats()
5670 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5680 int nchan = adap->params.arch.nchan; in t4_tp_get_cpl_stats()
5682 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok); in t4_tp_get_cpl_stats()
5684 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok); in t4_tp_get_cpl_stats()
5688 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5698 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A, in t4_tp_get_rdma_stats()
5703 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5716 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx, in t4_get_fcoe_stats()
5719 t4_tp_mib_read(adap, &st->frames_drop, 1, in t4_get_fcoe_stats()
5725 st->octets_ddp = ((u64)val[0] << 32) | val[1]; in t4_get_fcoe_stats()
5729 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5734 * Returns the values of TP's counters for non-TCP directly-placed packets.
5742 st->frames = val[0]; in t4_get_usm_stats()
5743 st->drops = val[1]; in t4_get_usm_stats()
5744 st->octets = ((u64)val[2] << 32) | val[3]; in t4_get_usm_stats()
5748 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5751 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5771 * t4_read_cong_tbl - reads the congestion control table
5792 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5794 * @addr: the indirect TP register address
5800 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, in t4_tp_wr_bits_indirect() argument
5803 t4_write_reg(adap, TP_PIO_ADDR_A, addr); in t4_tp_wr_bits_indirect()
5809 * init_cong_ctrl - initialize congestion control parameters
5856 * t4_load_mtus - write the MTU and congestion control HW tables
5862 * Write the HW MTU table with the supplied MTUs and the high-speed
5883 log2--; in t4_load_mtus()
5890 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], in t4_load_mtus()
5899 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5910 u64 v = bytes256 * adap->params.vpd.cclk; in chan_rate()
5916 * t4_get_chan_txrate - get the current per channel Tx rates
5931 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5939 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5946 * t4_set_trace_filter - configure one of the tracing filters
5973 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) in t4_set_trace_filter()
5974 return -EINVAL; in t4_set_trace_filter()
5980 if (tp->snap_len > 9600 || idx) in t4_set_trace_filter()
5981 return -EINVAL; in t4_set_trace_filter()
5984 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
5985 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M || in t4_set_trace_filter()
5986 tp->min_len > TFMINPKTSIZE_M) in t4_set_trace_filter()
5987 return -EINVAL; in t4_set_trace_filter()
5992 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A); in t4_set_trace_filter()
5997 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
5998 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
6001 TFCAPTUREMAX_V(tp->snap_len) | in t4_set_trace_filter()
6002 TFMINPKTSIZE_V(tp->min_len)); in t4_set_trace_filter()
6004 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) | in t4_set_trace_filter()
6005 (is_t4(adap->params.chip) ? in t4_set_trace_filter()
6006 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) : in t4_set_trace_filter()
6007 T5_TFPORT_V(tp->port) | T5_TFEN_F | in t4_set_trace_filter()
6008 T5_TFINVERTMATCH_V(tp->invert))); in t4_set_trace_filter()
6014 * t4_get_trace_filter - query one of the tracing filters
6018 * @enabled: non-zero if the filter is enabled
6032 if (is_t4(adap->params.chip)) { in t4_get_trace_filter()
6034 tp->port = TFPORT_G(ctla); in t4_get_trace_filter()
6035 tp->invert = !!(ctla & TFINVERTMATCH_F); in t4_get_trace_filter()
6038 tp->port = T5_TFPORT_G(ctla); in t4_get_trace_filter()
6039 tp->invert = !!(ctla & T5_TFINVERTMATCH_F); in t4_get_trace_filter()
6041 tp->snap_len = TFCAPTUREMAX_G(ctlb); in t4_get_trace_filter()
6042 tp->min_len = TFMINPKTSIZE_G(ctlb); in t4_get_trace_filter()
6043 tp->skip_ofst = TFOFFSET_G(ctla); in t4_get_trace_filter()
6044 tp->skip_len = TFLENGTH_G(ctla); in t4_get_trace_filter()
6046 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx; in t4_get_trace_filter()
6051 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
6052 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
6057 * t4_pmtx_get_stats - returns the HW stats from PMTX
6069 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmtx_get_stats()
6072 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
6084 * t4_pmrx_get_stats - returns the HW stats from PMRX
6096 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmrx_get_stats()
6099 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
6111 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6124 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in compute_mps_bg_map()
6144 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n", in compute_mps_bg_map()
6151 * t4_get_mps_bg_map - return the buffer groups associated with a port
6173 mps_bg_map = adapter->params.mps_bg_map; in t4_get_mps_bg_map()
6187 if (adapter->flags & CXGB4_FW_OK) { in t4_get_mps_bg_map()
6193 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf, in t4_get_mps_bg_map()
6217 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6239 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf, in t4_get_tp_e2c_map()
6248 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6258 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_tp_ch_map()
6262 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n", in t4_get_tp_ch_map()
6289 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n", in t4_get_tp_ch_map()
6295 * t4_get_port_type_description - return Port Type string description
6332 * t4_get_port_stats_offset - collect port stats relative to a previous
6350 *s -= *o; in t4_get_port_stats_offset()
6354 * t4_get_port_stats - collect port statistics
6368 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
6372 p->tx_octets = GET_STAT(TX_PORT_BYTES); in t4_get_port_stats()
6373 p->tx_frames = GET_STAT(TX_PORT_FRAMES); in t4_get_port_stats()
6374 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); in t4_get_port_stats()
6375 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); in t4_get_port_stats()
6376 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); in t4_get_port_stats()
6377 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); in t4_get_port_stats()
6378 p->tx_frames_64 = GET_STAT(TX_PORT_64B); in t4_get_port_stats()
6379 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); in t4_get_port_stats()
6380 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); in t4_get_port_stats()
6381 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); in t4_get_port_stats()
6382 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); in t4_get_port_stats()
6383 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); in t4_get_port_stats()
6384 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); in t4_get_port_stats()
6385 p->tx_drop = GET_STAT(TX_PORT_DROP); in t4_get_port_stats()
6386 p->tx_pause = GET_STAT(TX_PORT_PAUSE); in t4_get_port_stats()
6387 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); in t4_get_port_stats()
6388 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); in t4_get_port_stats()
6389 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); in t4_get_port_stats()
6390 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); in t4_get_port_stats()
6391 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); in t4_get_port_stats()
6392 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); in t4_get_port_stats()
6393 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); in t4_get_port_stats()
6394 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); in t4_get_port_stats()
6396 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6398 p->tx_frames_64 -= p->tx_pause; in t4_get_port_stats()
6400 p->tx_mcast_frames -= p->tx_pause; in t4_get_port_stats()
6402 p->rx_octets = GET_STAT(RX_PORT_BYTES); in t4_get_port_stats()
6403 p->rx_frames = GET_STAT(RX_PORT_FRAMES); in t4_get_port_stats()
6404 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); in t4_get_port_stats()
6405 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); in t4_get_port_stats()
6406 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); in t4_get_port_stats()
6407 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); in t4_get_port_stats()
6408 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); in t4_get_port_stats()
6409 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); in t4_get_port_stats()
6410 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); in t4_get_port_stats()
6411 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); in t4_get_port_stats()
6412 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); in t4_get_port_stats()
6413 p->rx_frames_64 = GET_STAT(RX_PORT_64B); in t4_get_port_stats()
6414 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); in t4_get_port_stats()
6415 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); in t4_get_port_stats()
6416 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); in t4_get_port_stats()
6417 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); in t4_get_port_stats()
6418 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); in t4_get_port_stats()
6419 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); in t4_get_port_stats()
6420 p->rx_pause = GET_STAT(RX_PORT_PAUSE); in t4_get_port_stats()
6421 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); in t4_get_port_stats()
6422 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); in t4_get_port_stats()
6423 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); in t4_get_port_stats()
6424 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); in t4_get_port_stats()
6425 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); in t4_get_port_stats()
6426 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); in t4_get_port_stats()
6427 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); in t4_get_port_stats()
6428 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); in t4_get_port_stats()
6430 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6432 p->rx_frames_64 -= p->rx_pause; in t4_get_port_stats()
6434 p->rx_mcast_frames -= p->rx_pause; in t4_get_port_stats()
6437 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6438 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6439 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6440 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6441 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6442 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6443 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6444 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6451 * t4_get_lb_stats - collect loopback port statistics
6464 (is_t4(adap->params.chip) ? \ in t4_get_lb_stats()
6469 p->octets = GET_STAT(BYTES); in t4_get_lb_stats()
6470 p->frames = GET_STAT(FRAMES); in t4_get_lb_stats()
6471 p->bcast_frames = GET_STAT(BCAST); in t4_get_lb_stats()
6472 p->mcast_frames = GET_STAT(MCAST); in t4_get_lb_stats()
6473 p->ucast_frames = GET_STAT(UCAST); in t4_get_lb_stats()
6474 p->error_frames = GET_STAT(ERROR); in t4_get_lb_stats()
6476 p->frames_64 = GET_STAT(64B); in t4_get_lb_stats()
6477 p->frames_65_127 = GET_STAT(65B_127B); in t4_get_lb_stats()
6478 p->frames_128_255 = GET_STAT(128B_255B); in t4_get_lb_stats()
6479 p->frames_256_511 = GET_STAT(256B_511B); in t4_get_lb_stats()
6480 p->frames_512_1023 = GET_STAT(512B_1023B); in t4_get_lb_stats()
6481 p->frames_1024_1518 = GET_STAT(1024B_1518B); in t4_get_lb_stats()
6482 p->frames_1519_max = GET_STAT(1519B_MAX); in t4_get_lb_stats()
6483 p->drop = GET_STAT(DROP_FRAMES); in t4_get_lb_stats()
6485 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6486 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6487 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6488 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6489 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6490 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6491 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6492 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6498 /* t4_mk_filtdelwr - create a delete filter WR
6509 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR)); in t4_mk_filtdelwr()
6510 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16)); in t4_mk_filtdelwr()
6511 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) | in t4_mk_filtdelwr()
6513 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F); in t4_mk_filtdelwr()
6515 wr->rx_chan_rx_rpl_iq = in t4_mk_filtdelwr()
6527 u32 addr, u32 val) in t4_fwaddrspace_write() argument
6539 c.u.addrval.addr = cpu_to_be32(addr); in t4_fwaddrspace_write()
6546 * t4_mdio_rd - read a PHY register through MDIO
6580 * t4_mdio_wr - write a PHY register through MDIO
6611 * t4_sge_decode_idma_state - decode the idma state
6613 * @state: the state idma is stuck in
6730 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_sge_decode_idma_state()
6752 dev_err(adapter->pdev_dev, in t4_sge_decode_idma_state()
6757 if (is_t4(adapter->params.chip)) { in t4_sge_decode_idma_state()
6766 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); in t4_sge_decode_idma_state()
6768 CH_WARN(adapter, "idma state %d unknown\n", state); in t4_sge_decode_idma_state()
6776 * t4_sge_ctxt_flush - flush the SGE context cache
6805 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6825 nparams = ndbqtimers - dbqtimerix; in t4_read_sge_dbqtimers()
6834 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, in t4_read_sge_dbqtimers()
6846 * t4_fw_hello - establish communication with FW
6851 * @state: returns the current device state (if non-NULL)
6886 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) in t4_fw_hello()
6908 * Note that we also do this wait if we're a non-Master-capable PF and in t4_fw_hello()
6930 waiting -= 50; in t4_fw_hello()
6941 if (retries-- > 0) in t4_fw_hello()
6944 return -ETIMEDOUT; in t4_fw_hello()
6976 * t4_fw_bye - end communication with FW
6992 * t4_init_cmd - ask FW to initialize the device
7009 * t4_fw_reset - issue a reset to FW
7027 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7087 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7145 return -ETIMEDOUT; in t4_fw_restart()
7151 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7178 return -EINVAL; in t4_fw_upgrade()
7183 adap->flags &= ~CXGB4_FW_OK; in t4_fw_upgrade()
7198 * portion of the FLASH . The user will need to re-FLASH a new in t4_fw_upgrade()
7212 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); in t4_fw_upgrade()
7222 adap->flags |= CXGB4_FW_OK; in t4_fw_upgrade()
7227 * t4_fl_pkt_align - return the fl packet alignment
7254 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_fl_pkt_align()
7262 if (!is_t4(adap->params.chip)) { in t4_fl_pkt_align()
7280 * t4_fixup_host_params - fix up host-dependent parameters
7292 unsigned int page_shift = fls(page_size) - 1; in t4_fixup_host_params()
7293 unsigned int sge_hps = page_shift - 10; in t4_fixup_host_params()
7296 unsigned int fl_align_log = fls(fl_align) - 1; in t4_fixup_host_params()
7308 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
7312 INGPADBOUNDARY_V(fl_align_log - in t4_fixup_host_params()
7330 * Line Size, that'll involve a Read-Modify-Write cycle on the in t4_fixup_host_params()
7337 * Boundary to incorporate the PCI-E Maximum Payload Size. We in t4_fixup_host_params()
7342 if (pci_is_pcie(adap->pdev)) { in t4_fixup_host_params()
7350 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, in t4_fixup_host_params()
7370 unsigned int pack_align_log = fls(pack_align) - 1; in t4_fixup_host_params()
7372 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X; in t4_fixup_host_params()
7381 if (is_t5(adap->params.chip)) in t4_fixup_host_params()
7409 * For the single-MTU buffers in unpacked mode we need to include in t4_fixup_host_params()
7418 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
7419 & ~(fl_align-1)); in t4_fixup_host_params()
7421 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
7422 & ~(fl_align-1)); in t4_fixup_host_params()
7424 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
7430 * t4_fw_initialize - ask FW to initialize the device
7447 * t4_query_params_rw - query FW or device parameters
7470 return -EINVAL; in t4_query_params_rw()
7510 * t4_set_params_timeout - sets FW or device parameters
7532 return -EINVAL; in t4_set_params_timeout()
7541 while (nparams--) { in t4_set_params_timeout()
7550 * t4_set_params - sets FW or device parameters
7571 * t4_cfg_pfvf - configure PF/VF resource limits
7578 * @rxqi: the max number of interrupt-capable ingress queues
7619 * t4_alloc_vi - allocate a virtual interface
7635 * Returns a negative error number or the non-negative VI id.
7650 c.nmac = nmac - 1; in t4_alloc_vi()
7685 * t4_free_vi - free a virtual interface
7712 * t4_set_rxmode - set Rx properties of a virtual interface
7717 * @mtu: the new MTU or -1
7718 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7719 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7720 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7721 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7777 * t4_free_encap_mac_filt - frees MPS entry at given index
7791 u8 addr[] = {0, 0, 0, 0, 0, 0}; in t4_free_encap_mac_filt() local
7806 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_free_encap_mac_filt()
7808 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_free_encap_mac_filt()
7809 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_encap_mac_filt()
7814 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7817 * @addr: the MAC address
7829 const u8 *addr, const u8 *mask, unsigned int idx, in t4_free_raw_mac_filt() argument
7846 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) | in t4_free_raw_mac_filt()
7850 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) | in t4_free_raw_mac_filt()
7853 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) | in t4_free_raw_mac_filt()
7857 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN); in t4_free_raw_mac_filt()
7858 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); in t4_free_raw_mac_filt()
7860 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_raw_mac_filt()
7864 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7867 * @addr: the MAC address
7880 const u8 *addr, const u8 *mask, unsigned int vni, in t4_alloc_encap_mac_filt() argument
7896 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_alloc_encap_mac_filt()
7898 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_alloc_encap_mac_filt()
7899 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); in t4_alloc_encap_mac_filt()
7901 p->lookup_type_to_vni = in t4_alloc_encap_mac_filt()
7905 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask)); in t4_alloc_encap_mac_filt()
7906 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_encap_mac_filt()
7908 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); in t4_alloc_encap_mac_filt()
7913 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7916 * @addr: the MAC address
7928 const u8 *addr, const u8 *mask, unsigned int idx, in t4_alloc_raw_mac_filt() argument
7945 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx)); in t4_alloc_raw_mac_filt()
7948 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) | in t4_alloc_raw_mac_filt()
7951 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) | in t4_alloc_raw_mac_filt()
7955 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN); in t4_alloc_raw_mac_filt()
7956 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); in t4_alloc_raw_mac_filt()
7958 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_raw_mac_filt()
7960 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd)); in t4_alloc_raw_mac_filt()
7962 ret = -ENOMEM; in t4_alloc_raw_mac_filt()
7969 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7975 * @addr: the MAC address(es)
7980 * Allocates an exact-match filter for each of the supplied addresses and
7992 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) in t4_alloc_mac_filt() argument
7997 unsigned int max_naddr = adap->params.arch.mps_tcam_size; in t4_alloc_mac_filt()
8001 return -EINVAL; in t4_alloc_mac_filt()
8022 p->valid_to_idx = in t4_alloc_mac_filt()
8026 memcpy(p->macaddr, addr[offset + i], in t4_alloc_mac_filt()
8027 sizeof(p->macaddr)); in t4_alloc_mac_filt()
8035 if (ret && ret != -FW_ENOMEM) in t4_alloc_mac_filt()
8040 be16_to_cpu(p->valid_to_idx)); in t4_alloc_mac_filt()
8049 hash_mac_addr(addr[offset + i])); in t4_alloc_mac_filt()
8054 rem -= fw_naddr; in t4_alloc_mac_filt()
8057 if (ret == 0 || ret == -FW_ENOMEM) in t4_alloc_mac_filt()
8063 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8068 * @addr: the MAC address(es)
8071 * Frees the exact-match filter for each of the supplied addresses
8077 const u8 **addr, bool sleep_ok) in t4_free_mac_filt() argument
8082 unsigned int max_naddr = is_t4(adap->params.chip) ? in t4_free_mac_filt()
8088 return -EINVAL; in t4_free_mac_filt()
8110 p->valid_to_idx = cpu_to_be16( in t4_free_mac_filt()
8113 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_free_mac_filt()
8122 be16_to_cpu(p->valid_to_idx)); in t4_free_mac_filt()
8129 rem -= fw_naddr; in t4_free_mac_filt()
8138 * t4_change_mac - modifies the exact-match filter for a MAC address
8142 * @idx: index of existing filter for old value of MAC address, or -1
8143 * @addr: the new MAC address value
8147 * Modifies an exact-match filter and sets it to the new MAC address.
8151 * new address value. @idx can be -1 if the address is a new addition.
8157 int idx, const u8 *addr, bool persist, u8 *smt_idx) in t4_change_mac() argument
8162 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; in t4_change_mac()
8173 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_change_mac()
8176 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_change_mac()
8180 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); in t4_change_mac()
8182 ret = -ENOMEM; in t4_change_mac()
8184 if (adap->params.viid_smt_extn_support) { in t4_change_mac()
8193 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= in t4_change_mac()
8205 * t4_set_addr_hash - program the MAC inexact-match hash filter
8213 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8232 * t4_enable_vi_params - enable/disable a virtual interface
8260 * t4_enable_vi - enable/disable a virtual interface
8276 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8287 * we notify the OS-specific code of a potential Link Status change
8294 int ret = t4_enable_vi_params(adap, mbox, pi->viid, in t4_enable_pi_params()
8298 t4_os_link_changed(adap, pi->port_id, in t4_enable_pi_params()
8299 rx_en && tx_en && pi->link_cfg.link_ok); in t4_enable_pi_params()
8304 * t4_identify_port - identify a VI's port by blinking its LED
8327 * t4_iq_stop - stop an ingress queue and its FLs
8360 * t4_iq_free - free an ingress queue and its FLs
8391 * t4_eth_eq_free - free an Ethernet egress queue
8416 * t4_ctrl_eq_free - free a control egress queue
8441 * t4_ofld_eq_free - free an offload egress queue
8466 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8476 "Auto-negotiation Failure", in t4_link_down_rc_str()
8515 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8546 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8550 * 32-bit Port Capabilities value.
8557 * 16-bit Port Information message isn't the same as the in lstatus_to_fwcap()
8558 * 16-bit Port Capabilities bitfield used everywhere else ... in lstatus_to_fwcap()
8581 * t4_handle_get_port_info - process a FW reply message
8591 struct link_config *lc = &pi->link_cfg; in t4_handle_get_port_info()
8592 struct adapter *adapter = pi->adapter; in t4_handle_get_port_info()
8600 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16)); in t4_handle_get_port_info()
8603 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype); in t4_handle_get_port_info()
8609 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap)); in t4_handle_get_port_info()
8610 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap)); in t4_handle_get_port_info()
8611 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap)); in t4_handle_get_port_info()
8619 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32); in t4_handle_get_port_info()
8624 pcaps = be32_to_cpu(cmd->u.info32.pcaps32); in t4_handle_get_port_info()
8625 acaps = be32_to_cpu(cmd->u.info32.acaps32); in t4_handle_get_port_info()
8626 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32); in t4_handle_get_port_info()
8627 linkattr = be32_to_cpu(cmd->u.info32.linkattr32); in t4_handle_get_port_info()
8632 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n", in t4_handle_get_port_info()
8633 be32_to_cpu(cmd->action_to_len16)); in t4_handle_get_port_info()
8643 * whether the OS-dependent layer wants us to redo the current in t4_handle_get_port_info()
8646 lc->new_module = false; in t4_handle_get_port_info()
8647 lc->redo_l1cfg = false; in t4_handle_get_port_info()
8649 if (mod_type != pi->mod_type) { in t4_handle_get_port_info()
8653 * Speeds, Auto-Negotiation, Forward Error Correction, etc. in t4_handle_get_port_info()
8658 lc->pcaps = pcaps; in t4_handle_get_port_info()
8666 * the user explicitly requests these standards-based values. in t4_handle_get_port_info()
8668 lc->def_acaps = acaps; in t4_handle_get_port_info()
8680 pi->port_type = port_type; in t4_handle_get_port_info()
8684 pi->mod_type = mod_type; in t4_handle_get_port_info()
8686 /* Let the OS-dependent layer know if we have a new in t4_handle_get_port_info()
8689 lc->new_module = t4_is_inserted_mod_type(mod_type); in t4_handle_get_port_info()
8691 t4_os_portmod_changed(adapter, pi->port_id); in t4_handle_get_port_info()
8694 if (link_ok != lc->link_ok || speed != lc->speed || in t4_handle_get_port_info()
8695 fc != lc->fc || adv_fc != lc->advertised_fc || in t4_handle_get_port_info()
8696 fec != lc->fec) { in t4_handle_get_port_info()
8698 if (!link_ok && lc->link_ok) { in t4_handle_get_port_info()
8699 lc->link_down_rc = linkdnrc; in t4_handle_get_port_info()
8700 dev_warn_ratelimited(adapter->pdev_dev, in t4_handle_get_port_info()
8702 pi->tx_chan, in t4_handle_get_port_info()
8705 lc->link_ok = link_ok; in t4_handle_get_port_info()
8706 lc->speed = speed; in t4_handle_get_port_info()
8707 lc->advertised_fc = adv_fc; in t4_handle_get_port_info()
8708 lc->fc = fc; in t4_handle_get_port_info()
8709 lc->fec = fec; in t4_handle_get_port_info()
8711 lc->lpacaps = lpacaps; in t4_handle_get_port_info()
8712 lc->acaps = acaps & ADVERT_MASK; in t4_handle_get_port_info()
8714 /* If we're not physically capable of Auto-Negotiation, note in t4_handle_get_port_info()
8715 * this as Auto-Negotiation disabled. Otherwise, we track in t4_handle_get_port_info()
8716 * what Auto-Negotiation settings we have. Note parallel in t4_handle_get_port_info()
8719 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) { in t4_handle_get_port_info()
8720 lc->autoneg = AUTONEG_DISABLE; in t4_handle_get_port_info()
8721 } else if (lc->acaps & FW_PORT_CAP32_ANEG) { in t4_handle_get_port_info()
8722 lc->autoneg = AUTONEG_ENABLE; in t4_handle_get_port_info()
8728 lc->acaps = 0; in t4_handle_get_port_info()
8729 lc->speed_caps = fwcap_to_fwspeed(acaps); in t4_handle_get_port_info()
8730 lc->autoneg = AUTONEG_DISABLE; in t4_handle_get_port_info()
8733 t4_os_link_changed(adapter, pi->port_id, link_ok); in t4_handle_get_port_info()
8736 /* If we have a new Transceiver Module and the OS-dependent code has in t4_handle_get_port_info()
8740 if (lc->new_module && lc->redo_l1cfg) { in t4_handle_get_port_info()
8750 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc); in t4_handle_get_port_info()
8753 dev_warn(adapter->pdev_dev, in t4_handle_get_port_info()
8757 lc->new_module = false; in t4_handle_get_port_info()
8758 lc->redo_l1cfg = false; in t4_handle_get_port_info()
8762 * t4_update_port_info - retrieve and update port information if changed
8771 unsigned int fw_caps = pi->adapter->params.fw_caps_support; in t4_update_port_info()
8778 FW_PORT_CMD_PORTID_V(pi->tx_chan)); in t4_update_port_info()
8784 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox, in t4_update_port_info()
8794 * t4_get_link_params - retrieve basic link parameters for given port
8807 unsigned int fw_caps = pi->adapter->params.fw_caps_support; in t4_get_link_params()
8816 FW_PORT_CMD_PORTID_V(pi->tx_chan)); in t4_get_link_params()
8823 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox, in t4_get_link_params()
8855 * t4_handle_fw_rpl - process a FW reply message
8866 * conditionals ... We can get away with pre-dereferencing in t4_handle_fw_rpl()
8872 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16)); in t4_handle_fw_rpl()
8878 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid)); in t4_handle_fw_rpl()
8883 if (pi->tx_chan == chan) in t4_handle_fw_rpl()
8889 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", in t4_handle_fw_rpl()
8891 return -EINVAL; in t4_handle_fw_rpl()
8900 if (pci_is_pcie(adapter->pdev)) { in get_pci_mode()
8901 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); in get_pci_mode()
8902 p->speed = val & PCI_EXP_LNKSTA_CLS; in get_pci_mode()
8903 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; in get_pci_mode()
8908 * init_link_config - initialize a link's SW state
8914 * capabilities and default speed/flow-control/autonegotiation settings.
8919 lc->pcaps = pcaps; in init_link_config()
8920 lc->def_acaps = acaps; in init_link_config()
8921 lc->lpacaps = 0; in init_link_config()
8922 lc->speed_caps = 0; in init_link_config()
8923 lc->speed = 0; in init_link_config()
8924 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; in init_link_config()
8929 lc->requested_fec = FEC_AUTO; in init_link_config()
8930 lc->fec = fwcap_to_cc_fec(lc->def_acaps); in init_link_config()
8932 /* If the Port is capable of Auto-Negtotiation, initialize it as in init_link_config()
8935 * Auto-Negotiate disabled and select the highest supported speed in init_link_config()
8939 if (lc->pcaps & FW_PORT_CAP32_ANEG) { in init_link_config()
8940 lc->acaps = lc->pcaps & ADVERT_MASK; in init_link_config()
8941 lc->autoneg = AUTONEG_ENABLE; in init_link_config()
8942 lc->requested_fc |= PAUSE_AUTONEG; in init_link_config()
8944 lc->acaps = 0; in init_link_config()
8945 lc->autoneg = AUTONEG_DISABLE; in init_link_config()
8946 lc->speed_caps = fwcap_to_fwspeed(acaps); in init_link_config()
8962 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); in t4_wait_dev_ready()
8972 /* Table for non-Numonix supported flash parts. Numonix parts are left in t4_get_flash_params()
8997 /* Check to see if it's one of our non-standard supported Flash parts. in t4_get_flash_params()
9001 adap->params.sf_size = supported_flash[part].size_mb; in t4_get_flash_params()
9002 adap->params.sf_nsec = in t4_get_flash_params()
9003 adap->params.sf_size / SF_SEC_SIZE; in t4_get_flash_params()
9018 /* This Density -> Size decoding table is taken from Micron in t4_get_flash_params()
9053 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */ in t4_get_flash_params()
9054 /* This Density -> Size decoding table is taken from ISSI in t4_get_flash_params()
9069 /* This Density -> Size decoding table is taken from Macronix in t4_get_flash_params()
9084 /* This Density -> Size decoding table is taken from Winbond in t4_get_flash_params()
9107 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n", in t4_get_flash_params()
9113 adap->params.sf_size = size; in t4_get_flash_params()
9114 adap->params.sf_nsec = size / SF_SEC_SIZE; in t4_get_flash_params()
9117 if (adap->params.sf_size < FLASH_MIN_SIZE) in t4_get_flash_params()
9118 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n", in t4_get_flash_params()
9119 flashid, adap->params.sf_size, FLASH_MIN_SIZE); in t4_get_flash_params()
9124 * t4_prep_adapter - prepare SW and HW for operation
9137 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
9142 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); in t4_prep_adapter()
9148 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); in t4_prep_adapter()
9150 adapter->params.chip = 0; in t4_prep_adapter()
9153 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); in t4_prep_adapter()
9154 adapter->params.arch.sge_fl_db = DBPRIO_F; in t4_prep_adapter()
9155 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9157 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
9158 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
9159 adapter->params.arch.pm_stats_cnt = PM_NSTATS; in t4_prep_adapter()
9160 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
9164 adapter->params.arch.cng_ch_bits_log = 2; in t4_prep_adapter()
9167 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); in t4_prep_adapter()
9168 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; in t4_prep_adapter()
9169 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9171 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
9172 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
9173 adapter->params.arch.pm_stats_cnt = PM_NSTATS; in t4_prep_adapter()
9174 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
9175 adapter->params.arch.cng_ch_bits_log = 2; in t4_prep_adapter()
9178 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); in t4_prep_adapter()
9179 adapter->params.arch.sge_fl_db = 0; in t4_prep_adapter()
9180 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9182 adapter->params.arch.mps_rplc_size = 256; in t4_prep_adapter()
9183 adapter->params.arch.nchan = 2; in t4_prep_adapter()
9184 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS; in t4_prep_adapter()
9185 adapter->params.arch.vfcount = 256; in t4_prep_adapter()
9189 adapter->params.arch.cng_ch_bits_log = 3; in t4_prep_adapter()
9192 dev_err(adapter->pdev_dev, "Device %d is not supported\n", in t4_prep_adapter()
9194 return -EINVAL; in t4_prep_adapter()
9197 adapter->params.cim_la_size = CIMLA_SIZE; in t4_prep_adapter()
9198 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
9203 adapter->params.nports = 1; in t4_prep_adapter()
9204 adapter->params.portvec = 1; in t4_prep_adapter()
9205 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
9208 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2, in t4_prep_adapter()
9214 * t4_shutdown_adapter - shut down adapter, host & wire
9222 * the port Link Status to go down -- if register writes work --
9232 u32 a_port_cfg = is_t4(adapter->params.chip) ? in t4_shutdown_adapter()
9246 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9283 if (!user && is_t4(adapter->params.chip)) in t4_bar2_sge_qregs()
9284 return -EINVAL; in t4_bar2_sge_qregs()
9288 page_shift = adapter->params.sge.hps + 10; in t4_bar2_sge_qregs()
9294 ? adapter->params.sge.eq_qpp in t4_bar2_sge_qregs()
9295 : adapter->params.sge.iq_qpp); in t4_bar2_sge_qregs()
9296 qpp_mask = (1 << qpp_shift) - 1; in t4_bar2_sge_qregs()
9318 * from the writes to the registers -- the Write Combined Doorbell in t4_bar2_sge_qregs()
9336 * t4_init_devlog_params - initialize adapter->params.devlog
9344 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
9359 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams); in t4_init_devlog_params()
9360 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4; in t4_init_devlog_params()
9364 dparams->size = nentries * sizeof(struct fw_devlog_e); in t4_init_devlog_params()
9375 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
9382 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo); in t4_init_devlog_params()
9383 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4; in t4_init_devlog_params()
9384 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); in t4_init_devlog_params()
9390 * t4_init_sge_params - initialize adap->params.sge
9397 struct sge_params *sge_params = &adapter->params.sge; in t4_init_sge_params()
9405 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf); in t4_init_sge_params()
9406 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); in t4_init_sge_params()
9411 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf); in t4_init_sge_params()
9413 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); in t4_init_sge_params()
9415 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); in t4_init_sge_params()
9421 * t4_init_tp_params - initialize adap->params.tp
9434 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
9435 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
9437 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ in t4_init_tp_params()
9439 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
9449 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_init_tp_params()
9452 dev_info(adap->pdev_dev, in t4_init_tp_params()
9456 adap->params.tp.vlan_pri_map = in t4_init_tp_params()
9458 adap->params.tp.filter_mask = in t4_init_tp_params()
9461 dev_info(adap->pdev_dev, in t4_init_tp_params()
9462 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n"); in t4_init_tp_params()
9464 /* Incase of older-fw (which doesn't expose the api in t4_init_tp_params()
9465 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses in t4_init_tp_params()
9466 * the fw api) combination, fall-back to older method of reading in t4_init_tp_params()
9467 * the filter mode from indirect-register in t4_init_tp_params()
9469 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
9472 /* With the older-fw and newer-driver combination we might run in t4_init_tp_params()
9479 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map; in t4_init_tp_params()
9482 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
9488 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { in t4_init_tp_params()
9490 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0; in t4_init_tp_params()
9497 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F); in t4_init_tp_params()
9498 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
9499 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
9500 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
9501 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F); in t4_init_tp_params()
9502 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9504 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9506 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9508 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9510 adap->params.tp.frag_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9516 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
9517 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
9520 adap->params.tp.hash_filter_mask = v; in t4_init_tp_params()
9522 adap->params.tp.hash_filter_mask |= ((u64)v << 32); in t4_init_tp_params()
9527 * t4_filter_field_shift - calculate filter field shift
9537 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
9542 return -1; in t4_filter_field_shift()
9594 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid)); in t4_init_rss_mode()
9599 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); in t4_init_rss_mode()
9605 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9621 struct adapter *adapter = pi->adapter; in t4_init_portinfo()
9622 unsigned int fw_caps = adapter->params.fw_caps_support; in t4_init_portinfo()
9632 * which knows the new 32-bit Port Capabilities, it's time to find in t4_init_portinfo()
9634 * Updates using the new 32-bit Port Capabilities version of the in t4_init_portinfo()
9645 adapter->params.fw_caps_support = fw_caps; in t4_init_portinfo()
9657 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd); in t4_init_portinfo()
9669 : -1); in t4_init_portinfo()
9678 : -1); in t4_init_portinfo()
9683 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size, in t4_init_portinfo()
9688 pi->viid = ret; in t4_init_portinfo()
9689 pi->tx_chan = port; in t4_init_portinfo()
9690 pi->lport = port; in t4_init_portinfo()
9691 pi->rss_size = rss_size; in t4_init_portinfo()
9692 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port); in t4_init_portinfo()
9697 if (adapter->params.viid_smt_extn_support) { in t4_init_portinfo()
9698 pi->vivld = vivld; in t4_init_portinfo()
9699 pi->vin = vin; in t4_init_portinfo()
9702 pi->vivld = FW_VIID_VIVLD_G(pi->viid); in t4_init_portinfo()
9703 pi->vin = FW_VIID_VIN_G(pi->viid); in t4_init_portinfo()
9706 pi->port_type = port_type; in t4_init_portinfo()
9707 pi->mdio_addr = mdio_addr; in t4_init_portinfo()
9708 pi->mod_type = FW_PORT_MOD_TYPE_NA; in t4_init_portinfo()
9710 init_link_config(&pi->link_cfg, pcaps, acaps); in t4_init_portinfo()
9716 u8 addr[6]; in t4_port_init() local
9722 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
9725 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr); in t4_port_init()
9729 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); in t4_port_init()
9740 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL, in t4_init_port_mirror()
9752 * t4_read_cimq_cfg - read CIM queue configuration
9764 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
9771 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9774 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ in t4_read_cimq_cfg()
9780 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9787 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9791 * @n: capacity of @data in 32-bit words
9795 * error and the number of 32-bit words actually read on success.
9800 unsigned int addr; in t4_read_cim_ibq() local
9804 return -EINVAL; in t4_read_cim_ibq()
9806 addr = qid * nwords; in t4_read_cim_ibq()
9810 /* It might take 3-10ms before the IBQ debug read access is allowed. in t4_read_cim_ibq()
9815 for (i = 0; i < n; i++, addr++) { in t4_read_cim_ibq()
9816 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | in t4_read_cim_ibq()
9829 * t4_read_cim_obq - read the contents of a CIM outbound queue
9833 * @n: capacity of @data in 32-bit words
9837 * error and the number of 32-bit words actually read on success.
9842 unsigned int addr, v, nwords; in t4_read_cim_obq() local
9843 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
9846 if ((qid > (cim_num_obq - 1)) || (n & 3)) in t4_read_cim_obq()
9847 return -EINVAL; in t4_read_cim_obq()
9853 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ in t4_read_cim_obq()
9858 for (i = 0; i < n; i++, addr++) { in t4_read_cim_obq()
9859 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | in t4_read_cim_obq()
9872 * t4_cim_read - read a block from CIM internal address space
9874 * @addr: the start address within the CIM address space
9878 * Reads a block of 4-byte words from the CIM intenal address space.
9880 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_read() argument
9886 return -EBUSY; in t4_cim_read()
9888 for ( ; !ret && n--; addr += 4) { in t4_cim_read()
9889 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); in t4_cim_read()
9899 * t4_cim_write - write a block into CIM internal address space
9901 * @addr: the start address within the CIM address space
9905 * Writes a block of 4-byte words into the CIM intenal address space.
9907 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_write() argument
9913 return -EBUSY; in t4_cim_write()
9915 for ( ; !ret && n--; addr += 4) { in t4_cim_write()
9917 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); in t4_cim_write()
9924 static int t4_cim_write1(struct adapter *adap, unsigned int addr, in t4_cim_write1() argument
9927 return t4_cim_write(adap, addr, 1, &val); in t4_cim_write1()
9931 * t4_cim_read_la - read CIM LA capture buffer
9963 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
9972 ret = -ETIMEDOUT; in t4_cim_read_la()
9979 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to in t4_cim_read_la()
9980 * identify the 32-bit portion of the full 312-bit data in t4_cim_read_la()
9982 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9) in t4_cim_read_la()
10000 * t4_tp_read_la - read TP LA capture buffer
10017 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
10029 val |= adap->params.tp.la_mask; in t4_tp_read_la()
10039 la_buf[TPLA_SIZE - 1] = ~0ULL; in t4_tp_read_la()
10043 cfg | adap->params.tp.la_mask); in t4_tp_read_la()
10057 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10059 * @idma: the adapter IDMA Monitor state
10064 struct sge_idma_monitor_state *idma) in t4_idma_monitor_init() argument
10078 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ in t4_idma_monitor_init()
10079 idma->idma_stalled[0] = 0; in t4_idma_monitor_init()
10080 idma->idma_stalled[1] = 0; in t4_idma_monitor_init()
10084 * t4_idma_monitor - monitor SGE Ingress DMA state
10086 * @idma: the adapter IDMA Monitor state
10088 * @ticks: number of ticks since the last IDMA Monitor call
10091 struct sge_idma_monitor_state *idma, in t4_idma_monitor() argument
10101 * threshold they'll stay above that till the IDMA state changes. in t4_idma_monitor()
10116 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { in t4_idma_monitor()
10117 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz) in t4_idma_monitor()
10118 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, " in t4_idma_monitor()
10120 i, idma->idma_qid[i], in t4_idma_monitor()
10121 idma->idma_stalled[i] / hz); in t4_idma_monitor()
10122 idma->idma_stalled[i] = 0; in t4_idma_monitor()
10135 if (idma->idma_stalled[i] == 0) { in t4_idma_monitor()
10136 idma->idma_stalled[i] = hz; in t4_idma_monitor()
10137 idma->idma_warn[i] = 0; in t4_idma_monitor()
10139 idma->idma_stalled[i] += ticks; in t4_idma_monitor()
10140 idma->idma_warn[i] -= ticks; in t4_idma_monitor()
10143 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz) in t4_idma_monitor()
10148 if (idma->idma_warn[i] > 0) in t4_idma_monitor()
10150 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz; in t4_idma_monitor()
10152 /* Read and save the SGE IDMA State and Queue ID information. in t4_idma_monitor()
10158 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; in t4_idma_monitor()
10162 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; in t4_idma_monitor()
10164 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in " in t4_idma_monitor()
10166 i, idma->idma_qid[i], idma->idma_state[i], in t4_idma_monitor()
10167 idma->idma_stalled[i] / hz, in t4_idma_monitor()
10169 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); in t4_idma_monitor()
10174 * t4_load_cfg - download config file
10184 unsigned int addr; in t4_load_cfg() local
10186 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_cfg()
10192 addr = cfg_addr; in t4_load_cfg()
10193 flash_cfg_start_sec = addr / SF_SEC_SIZE; in t4_load_cfg()
10196 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n", in t4_load_cfg()
10198 return -EFBIG; in t4_load_cfg()
10204 flash_cfg_start_sec + i - 1); in t4_load_cfg()
10206 * with the on-adapter Firmware Configuration File. in t4_load_cfg()
10213 if ((size - i) < SF_PAGE_SIZE) in t4_load_cfg()
10214 n = size - i; in t4_load_cfg()
10217 ret = t4_write_flash(adap, addr, n, cfg_data); in t4_load_cfg()
10221 addr += SF_PAGE_SIZE; in t4_load_cfg()
10227 dev_err(adap->pdev_dev, "config file %s failed %d\n", in t4_load_cfg()
10233 * t4_set_vf_mac - Set MAC address for the specified VF
10237 * @addr: the MAC address(es) to be set to the specified VF
10240 unsigned int naddr, u8 *addr) in t4_set_vf_mac_acl() argument
10248 FW_ACL_MAC_CMD_PFN_V(adapter->pf) | in t4_set_vf_mac_acl()
10255 switch (adapter->pf) { in t4_set_vf_mac_acl()
10257 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); in t4_set_vf_mac_acl()
10260 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); in t4_set_vf_mac_acl()
10263 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); in t4_set_vf_mac_acl()
10266 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); in t4_set_vf_mac_acl()
10270 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); in t4_set_vf_mac_acl()
10274 * t4_read_pace_tbl - read the pace table
10292 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10304 unsigned int v, addr, bpt, cpt; in t4_get_tx_sched() local
10307 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2; in t4_get_tx_sched()
10308 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); in t4_get_tx_sched()
10316 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ in t4_get_tx_sched()
10321 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2; in t4_get_tx_sched()
10322 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); in t4_get_tx_sched()
10330 /* t4_sge_ctxt_rd - read an SGE context through FW
10370 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10419 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params()
10424 * t4_i2c_rd - read I2C data from adapter
10427 * @port: Port number if per-port device; <0 if not
10428 * @devid: per-port device ID or absolute device ID
10444 return -EINVAL; in t4_i2c_rd()
10448 return -EINVAL; in t4_i2c_rd()
10474 len -= i2c_len; in t4_i2c_rd()
10481 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10499 FW_ACL_VLAN_CMD_PFN_V(adap->pf) | in t4_set_vlan_acl()
10511 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); in t4_set_vlan_acl()
10515 * modify_device_id - Modifies the device ID of the Boot BIOS image
10531 pcir_offset = le16_to_cpu(header->pcir_offset); in modify_device_id()
10540 * 0x04-0xFF: Do not modify in modify_device_id()
10542 if (pcir_header->code_type == CXGB4_HDR_CODE1) { in modify_device_id()
10549 pcir_header->device_id = cpu_to_le16(device_id); in modify_device_id()
10555 header->cksum = 0x0; in modify_device_id()
10560 for (i = 0; i < (header->size512 * 512); i++) in modify_device_id()
10567 cur_header[7] = -csum; in modify_device_id()
10569 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) { in modify_device_id()
10573 pcir_header->device_id = cpu_to_le16(device_id); in modify_device_id()
10579 cur_header += header->size512 * 512; in modify_device_id()
10580 } while (!(pcir_header->indicator & CXGB4_HDR_INDI)); in modify_device_id()
10584 * t4_load_boot - download boot flash
10591 * The boot image has the following sections: a 28-byte header and the
10597 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_boot()
10604 int ret, addr; in t4_load_boot() local
10610 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n"); in t4_load_boot()
10611 return -EFBIG; in t4_load_boot()
10616 pcir_offset = le16_to_cpu(header->pcir_offset); in t4_load_boot()
10626 dev_err(adap->pdev_dev, "boot image too small/large\n"); in t4_load_boot()
10627 return -EFBIG; in t4_load_boot()
10630 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) { in t4_load_boot()
10631 dev_err(adap->pdev_dev, "Boot image missing signature\n"); in t4_load_boot()
10632 return -EINVAL; in t4_load_boot()
10636 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) { in t4_load_boot()
10637 dev_err(adap->pdev_dev, "PCI header missing signature\n"); in t4_load_boot()
10638 return -EINVAL; in t4_load_boot()
10642 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) { in t4_load_boot()
10643 dev_err(adap->pdev_dev, "Vendor ID missing signature\n"); in t4_load_boot()
10644 return -EINVAL; in t4_load_boot()
10648 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, in t4_load_boot()
10654 (boot_sector >> 16) + i - 1); in t4_load_boot()
10658 * with the on-adapter option ROM file in t4_load_boot()
10663 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id); in t4_load_boot()
10668 if (le16_to_cpu(pcir_header->device_id) != device_id) { in t4_load_boot()
10682 addr = boot_sector; in t4_load_boot()
10683 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_boot()
10684 addr += SF_PAGE_SIZE; in t4_load_boot()
10686 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data); in t4_load_boot()
10696 dev_err(adap->pdev_dev, "boot image load failed, error %d\n", in t4_load_boot()
10702 * t4_flash_bootcfg_addr - return the address of the flash
10716 if (adapter->params.sf_size < in t4_flash_bootcfg_addr()
10718 return -ENOSPC; in t4_flash_bootcfg_addr()
10725 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_bootcfg()
10728 unsigned int addr, npad; in t4_load_bootcfg() local
10735 addr = cfg_addr; in t4_load_bootcfg()
10736 flash_cfg_start_sec = addr / SF_SEC_SIZE; in t4_load_bootcfg()
10739 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n", in t4_load_bootcfg()
10741 return -EFBIG; in t4_load_bootcfg()
10745 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) { in t4_load_bootcfg()
10746 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n"); in t4_load_bootcfg()
10747 ret = -EINVAL; in t4_load_bootcfg()
10754 flash_cfg_start_sec + i - 1); in t4_load_bootcfg()
10758 * with the on-adapter OptionROM Configuration File. in t4_load_bootcfg()
10765 n = min_t(u32, size - i, SF_PAGE_SIZE); in t4_load_bootcfg()
10767 ret = t4_write_flash(adap, addr, n, cfg_data); in t4_load_bootcfg()
10771 addr += SF_PAGE_SIZE; in t4_load_bootcfg()
10775 npad = ((size + 4 - 1) & ~3) - size; in t4_load_bootcfg()
10786 dev_err(adap->pdev_dev, "boot config data %s failed %d\n", in t4_load_bootcfg()