Lines Matching refs:padap
477 struct adapter *padap = pdbg_init->adap; in is_fw_attached() local
479 if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd) in is_fw_attached()
514 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len, in cudbg_read_vpd_reg() argument
519 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE); in cudbg_read_vpd_reg()
523 rc = pci_read_vpd(padap->pdev, vaddr, len, dest); in cudbg_read_vpd_reg()
536 int cudbg_fill_meminfo(struct adapter *padap, in cudbg_fill_meminfo() argument
557 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); in cudbg_fill_meminfo()
559 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); in cudbg_fill_meminfo()
570 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); in cudbg_fill_meminfo()
580 if (is_t5(padap->params.chip)) { in cudbg_fill_meminfo()
582 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); in cudbg_fill_meminfo()
593 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); in cudbg_fill_meminfo()
604 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); in cudbg_fill_meminfo()
615 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); in cudbg_fill_meminfo()
632 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); in cudbg_fill_meminfo()
633 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); in cudbg_fill_meminfo()
634 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); in cudbg_fill_meminfo()
635 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); in cudbg_fill_meminfo()
636 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); in cudbg_fill_meminfo()
637 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); in cudbg_fill_meminfo()
638 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); in cudbg_fill_meminfo()
639 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); in cudbg_fill_meminfo()
640 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); in cudbg_fill_meminfo()
643 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); in cudbg_fill_meminfo()
645 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) * in cudbg_fill_meminfo()
646 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A)); in cudbg_fill_meminfo()
649 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); in cudbg_fill_meminfo()
651 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) * in cudbg_fill_meminfo()
652 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A)); in cudbg_fill_meminfo()
655 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) { in cudbg_fill_meminfo()
656 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) { in cudbg_fill_meminfo()
657 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4; in cudbg_fill_meminfo()
658 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); in cudbg_fill_meminfo()
660 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); in cudbg_fill_meminfo()
661 md->base = t4_read_reg(padap, in cudbg_fill_meminfo()
672 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ in cudbg_fill_meminfo()
673 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ in cudbg_fill_meminfo()
687 if (!is_t4(padap->params.chip)) { in cudbg_fill_meminfo()
688 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A); in cudbg_fill_meminfo()
689 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A); in cudbg_fill_meminfo()
692 if (is_t5(padap->params.chip)) { in cudbg_fill_meminfo()
700 md->base = BASEADDR_G(t4_read_reg(padap, in cudbg_fill_meminfo()
708 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); in cudbg_fill_meminfo()
711 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); in cudbg_fill_meminfo()
715 md->base = padap->vres.ocq.start; in cudbg_fill_meminfo()
716 if (padap->vres.ocq.size) in cudbg_fill_meminfo()
717 md->limit = md->base + padap->vres.ocq.size - 1; in cudbg_fill_meminfo()
737 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A); in cudbg_fill_meminfo()
738 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; in cudbg_fill_meminfo()
742 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A); in cudbg_fill_meminfo()
743 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; in cudbg_fill_meminfo()
747 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A); in cudbg_fill_meminfo()
750 FREERXPAGECOUNT_G(t4_read_reg(padap, in cudbg_fill_meminfo()
755 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10; in cudbg_fill_meminfo()
758 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A); in cudbg_fill_meminfo()
759 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A); in cudbg_fill_meminfo()
762 FREETXPAGECOUNT_G(t4_read_reg(padap, in cudbg_fill_meminfo()
772 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A); in cudbg_fill_meminfo()
774 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A)); in cudbg_fill_meminfo()
777 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) in cudbg_fill_meminfo()
778 lo = t4_read_reg(padap, in cudbg_fill_meminfo()
781 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4); in cudbg_fill_meminfo()
782 if (is_t5(padap->params.chip)) { in cudbg_fill_meminfo()
793 for (i = 0; i < padap->params.arch.nchan; i++) { in cudbg_fill_meminfo()
794 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) in cudbg_fill_meminfo()
795 lo = t4_read_reg(padap, in cudbg_fill_meminfo()
798 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4); in cudbg_fill_meminfo()
799 if (is_t5(padap->params.chip)) { in cudbg_fill_meminfo()
817 struct adapter *padap = pdbg_init->adap; in cudbg_collect_reg_dump() local
822 if (is_t4(padap->params.chip)) in cudbg_collect_reg_dump()
824 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip)) in cudbg_collect_reg_dump()
830 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size); in cudbg_collect_reg_dump()
838 struct adapter *padap = pdbg_init->adap; in cudbg_collect_fw_devlog() local
843 rc = t4_init_devlog_params(padap); in cudbg_collect_fw_devlog()
849 dparams = &padap->params.devlog; in cudbg_collect_fw_devlog()
856 spin_lock(&padap->win0_lock); in cudbg_collect_fw_devlog()
857 rc = t4_memory_rw(padap, padap->params.drv_memwin, in cudbg_collect_fw_devlog()
862 spin_unlock(&padap->win0_lock); in cudbg_collect_fw_devlog()
876 struct adapter *padap = pdbg_init->adap; in cudbg_collect_cim_la() local
881 if (is_t6(padap->params.chip)) { in cudbg_collect_cim_la()
882 size = padap->params.cim_la_size / 10 + 1; in cudbg_collect_cim_la()
885 size = padap->params.cim_la_size / 8; in cudbg_collect_cim_la()
894 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg); in cudbg_collect_cim_la()
902 rc = t4_cim_read_la(padap, in cudbg_collect_cim_la()
917 struct adapter *padap = pdbg_init->adap; in cudbg_collect_cim_ma_la() local
926 t4_cim_read_ma_la(padap, in cudbg_collect_cim_ma_la()
937 struct adapter *padap = pdbg_init->adap; in cudbg_collect_cim_qcfg() local
948 cim_qcfg_data->chip = padap->params.chip; in cudbg_collect_cim_qcfg()
949 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A, in cudbg_collect_cim_qcfg()
957 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A, in cudbg_collect_cim_qcfg()
966 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, in cudbg_collect_cim_qcfg()
975 struct adapter *padap = pdbg_init->adap; in cudbg_read_cim_ibq() local
987 no_of_read_words = t4_read_cim_ibq(padap, qid, in cudbg_read_cim_ibq()
1044 u32 cudbg_cim_obq_size(struct adapter *padap, int qid) in cudbg_cim_obq_size() argument
1048 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in cudbg_cim_obq_size()
1050 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A); in cudbg_cim_obq_size()
1059 struct adapter *padap = pdbg_init->adap; in cudbg_read_cim_obq() local
1065 qsize = cudbg_cim_obq_size(padap, qid); in cudbg_read_cim_obq()
1071 no_of_read_words = t4_read_cim_obq(padap, qid, in cudbg_read_cim_obq()
1142 static int cudbg_meminfo_get_mem_index(struct adapter *padap, in cudbg_meminfo_get_mem_index() argument
1157 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG; in cudbg_meminfo_get_mem_index()
1180 static int cudbg_get_mem_region(struct adapter *padap, in cudbg_get_mem_region() argument
1189 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc); in cudbg_get_mem_region()
1231 static int cudbg_get_mem_relative(struct adapter *padap, in cudbg_get_mem_relative() argument
1238 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx); in cudbg_get_mem_relative()
1256 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type, in cudbg_get_payload_range() argument
1264 rc = cudbg_fill_meminfo(padap, &meminfo); in cudbg_get_payload_range()
1268 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name, in cudbg_get_payload_range()
1279 return cudbg_get_mem_relative(padap, &meminfo, mem_type, in cudbg_get_payload_range()
1373 struct adapter *padap = pdbg_init->adap; in cudbg_read_fw_mem() local
1383 rc = cudbg_get_payload_range(padap, mem_type, region_name[i], in cudbg_read_fw_mem()
1421 spin_lock(&padap->win0_lock); in cudbg_read_fw_mem()
1424 spin_unlock(&padap->win0_lock); in cudbg_read_fw_mem()
1447 struct adapter *padap = pdbg_init->adap; in cudbg_t4_fwcache() local
1452 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH); in cudbg_t4_fwcache()
1462 struct adapter *padap = pdbg_init->adap; in cudbg_mem_region_size() local
1468 rc = cudbg_fill_meminfo(padap, &mem_info); in cudbg_mem_region_size()
1475 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx); in cudbg_mem_region_size()
1548 struct adapter *padap = pdbg_init->adap; in cudbg_collect_rss() local
1552 nentries = t4_chip_rss_size(padap); in cudbg_collect_rss()
1558 rc = t4_read_rss(padap, (u16 *)temp_buff.data); in cudbg_collect_rss()
1571 struct adapter *padap = pdbg_init->adap; in cudbg_collect_rss_vf_config() local
1576 vf_count = padap->params.arch.vfcount; in cudbg_collect_rss_vf_config()
1585 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl, in cudbg_collect_rss_vf_config()
1594 struct adapter *padap = pdbg_init->adap; in cudbg_collect_path_mtu() local
1603 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL); in cudbg_collect_path_mtu()
1611 struct adapter *padap = pdbg_init->adap; in cudbg_collect_pm_stats() local
1622 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc); in cudbg_collect_pm_stats()
1623 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc); in cudbg_collect_pm_stats()
1631 struct adapter *padap = pdbg_init->adap; in cudbg_collect_hw_sched() local
1636 if (!padap->params.vpd.cclk) in cudbg_collect_hw_sched()
1646 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A); in cudbg_collect_hw_sched()
1647 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A)); in cudbg_collect_hw_sched()
1648 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab); in cudbg_collect_hw_sched()
1650 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i], in cudbg_collect_hw_sched()
1659 struct adapter *padap = pdbg_init->adap; in cudbg_collect_tp_indirect() local
1665 if (is_t5(padap->params.chip)) in cudbg_collect_tp_indirect()
1683 if (is_t5(padap->params.chip)) in cudbg_collect_tp_indirect()
1685 else if (is_t6(padap->params.chip)) in cudbg_collect_tp_indirect()
1692 if (is_t5(padap->params.chip)) { in cudbg_collect_tp_indirect()
1697 } else if (is_t6(padap->params.chip)) { in cudbg_collect_tp_indirect()
1703 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range, in cudbg_collect_tp_indirect()
1709 if (is_t5(padap->params.chip)) in cudbg_collect_tp_indirect()
1711 else if (is_t6(padap->params.chip)) in cudbg_collect_tp_indirect()
1718 if (is_t5(padap->params.chip)) { in cudbg_collect_tp_indirect()
1723 } else if (is_t6(padap->params.chip)) { in cudbg_collect_tp_indirect()
1729 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range, in cudbg_collect_tp_indirect()
1735 if (is_t5(padap->params.chip)) in cudbg_collect_tp_indirect()
1738 else if (is_t6(padap->params.chip)) in cudbg_collect_tp_indirect()
1746 if (is_t5(padap->params.chip)) { in cudbg_collect_tp_indirect()
1753 } else if (is_t6(padap->params.chip)) { in cudbg_collect_tp_indirect()
1761 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range, in cudbg_collect_tp_indirect()
1768 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap, in cudbg_read_sge_qbase_indirect_reg() argument
1784 t4_write_reg(padap, qbase->reg_addr, func); in cudbg_read_sge_qbase_indirect_reg()
1786 *buff = t4_read_reg(padap, qbase->reg_data[i]); in cudbg_read_sge_qbase_indirect_reg()
1793 struct adapter *padap = pdbg_init->adap; in cudbg_collect_sge_indirect() local
1814 t4_read_indirect(padap, in cudbg_collect_sge_indirect()
1823 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { in cudbg_collect_sge_indirect()
1834 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase, in cudbg_collect_sge_indirect()
1837 for (i = 0; i < padap->params.arch.vfcount; i++) in cudbg_collect_sge_indirect()
1838 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase, in cudbg_collect_sge_indirect()
1841 sge_qbase->vfcount = padap->params.arch.vfcount; in cudbg_collect_sge_indirect()
1851 struct adapter *padap = pdbg_init->adap; in cudbg_collect_ulprx_la() local
1862 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data); in cudbg_collect_ulprx_la()
1871 struct adapter *padap = pdbg_init->adap; in cudbg_collect_tp_la() local
1882 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A)); in cudbg_collect_tp_la()
1883 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL); in cudbg_collect_tp_la()
1891 struct adapter *padap = pdbg_init->adap; in cudbg_collect_meminfo() local
1911 rc = cudbg_fill_meminfo(padap, meminfo_buff); in cudbg_collect_meminfo()
1926 struct adapter *padap = pdbg_init->adap; in cudbg_collect_cim_pif_la() local
1938 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data, in cudbg_collect_cim_pif_la()
1948 struct adapter *padap = pdbg_init->adap; in cudbg_collect_clk_info() local
1954 if (!padap->params.vpd.cclk) in cudbg_collect_clk_info()
1963 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */ in cudbg_collect_clk_info()
1964 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A); in cudbg_collect_clk_info()
1971 t4_read_reg(padap, TP_DACK_TIMER_A); in cudbg_collect_clk_info()
1973 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A); in cudbg_collect_clk_info()
1975 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A); in cudbg_collect_clk_info()
1977 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A); in cudbg_collect_clk_info()
1979 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A); in cudbg_collect_clk_info()
1981 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A); in cudbg_collect_clk_info()
1983 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A); in cudbg_collect_clk_info()
1985 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A)); in cudbg_collect_clk_info()
1987 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A); in cudbg_collect_clk_info()
1996 struct adapter *padap = pdbg_init->adap; in cudbg_collect_pcie_indirect() local
2018 t4_read_indirect(padap, in cudbg_collect_pcie_indirect()
2037 t4_read_indirect(padap, in cudbg_collect_pcie_indirect()
2052 struct adapter *padap = pdbg_init->adap; in cudbg_collect_pm_indirect() local
2074 t4_read_indirect(padap, in cudbg_collect_pm_indirect()
2093 t4_read_indirect(padap, in cudbg_collect_pm_indirect()
2108 struct adapter *padap = pdbg_init->adap; in cudbg_collect_tid() local
2142 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); in cudbg_collect_tid()
2151 if (is_t5(padap->params.chip)) { in cudbg_collect_tid()
2152 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4; in cudbg_collect_tid()
2153 } else if (is_t6(padap->params.chip)) { in cudbg_collect_tid()
2155 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A); in cudbg_collect_tid()
2156 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A); in cudbg_collect_tid()
2160 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, in cudbg_collect_tid()
2174 tid->ntids = padap->tids.ntids; in cudbg_collect_tid()
2175 tid->nstids = padap->tids.nstids; in cudbg_collect_tid()
2176 tid->stid_base = padap->tids.stid_base; in cudbg_collect_tid()
2177 tid->hash_base = padap->tids.hash_base; in cudbg_collect_tid()
2179 tid->natids = padap->tids.natids; in cudbg_collect_tid()
2180 tid->nftids = padap->tids.nftids; in cudbg_collect_tid()
2181 tid->ftid_base = padap->tids.ftid_base; in cudbg_collect_tid()
2182 tid->aftid_base = padap->tids.aftid_base; in cudbg_collect_tid()
2183 tid->aftid_end = padap->tids.aftid_end; in cudbg_collect_tid()
2185 tid->sftid_base = padap->tids.sftid_base; in cudbg_collect_tid()
2186 tid->nsftids = padap->tids.nsftids; in cudbg_collect_tid()
2188 tid->flags = padap->flags; in cudbg_collect_tid()
2189 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A); in cudbg_collect_tid()
2190 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A); in cudbg_collect_tid()
2191 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A); in cudbg_collect_tid()
2200 struct adapter *padap = pdbg_init->adap; in cudbg_collect_pcie_config() local
2215 t4_hw_pci_read_cfg4(padap, j, value); in cudbg_collect_pcie_config()
2242 static int cudbg_get_ctxt_region_info(struct adapter *padap, in cudbg_get_ctxt_region_info() argument
2252 rc = cudbg_fill_meminfo(padap, &meminfo); in cudbg_get_ctxt_region_info()
2261 rc = cudbg_get_mem_region(padap, &meminfo, j, in cudbg_get_ctxt_region_info()
2266 rc = cudbg_get_mem_relative(padap, &meminfo, j, in cudbg_get_ctxt_region_info()
2285 value = t4_read_reg(padap, SGE_FLM_CFG_A); in cudbg_get_ctxt_region_info()
2301 int cudbg_dump_context_size(struct adapter *padap) in cudbg_dump_context_size() argument
2309 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); in cudbg_dump_context_size()
2330 struct adapter *padap = pdbg_init->adap; in cudbg_read_sge_ctxt() local
2341 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data); in cudbg_read_sge_ctxt()
2343 t4_sge_ctxt_rd_bd(padap, cid, ctype, data); in cudbg_read_sge_ctxt()
2379 struct adapter *padap = pdbg_init->adap; in cudbg_collect_dump_context() local
2389 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); in cudbg_collect_dump_context()
2393 rc = cudbg_dump_context_size(padap); in cudbg_collect_dump_context()
2437 t4_sge_ctxt_flush(padap, padap->mbox, i); in cudbg_collect_dump_context()
2439 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i], in cudbg_collect_dump_context()
2495 static void cudbg_mps_rpl_backdoor(struct adapter *padap, in cudbg_mps_rpl_backdoor() argument
2498 if (is_t5(padap->params.chip)) { in cudbg_mps_rpl_backdoor()
2499 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2501 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2503 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2505 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2508 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2510 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2512 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2514 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, in cudbg_mps_rpl_backdoor()
2517 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A)); in cudbg_mps_rpl_backdoor()
2518 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A)); in cudbg_mps_rpl_backdoor()
2519 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A)); in cudbg_mps_rpl_backdoor()
2520 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A)); in cudbg_mps_rpl_backdoor()
2526 struct adapter *padap = pdbg_init->adap; in cudbg_collect_tcam_index() local
2531 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) { in cudbg_collect_tcam_index()
2545 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); in cudbg_collect_tcam_index()
2546 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); in cudbg_collect_tcam_index()
2548 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); in cudbg_collect_tcam_index()
2549 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); in cudbg_collect_tcam_index()
2570 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); in cudbg_collect_tcam_index()
2571 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); in cudbg_collect_tcam_index()
2573 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); in cudbg_collect_tcam_index()
2574 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); in cudbg_collect_tcam_index()
2581 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx)); in cudbg_collect_tcam_index()
2582 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx)); in cudbg_collect_tcam_index()
2589 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx)); in cudbg_collect_tcam_index()
2590 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx)); in cudbg_collect_tcam_index()
2592 if (is_t5(padap->params.chip)) in cudbg_collect_tcam_index()
2594 else if (is_t6(padap->params.chip)) in cudbg_collect_tcam_index()
2615 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, in cudbg_collect_tcam_index()
2619 cudbg_mps_rpl_backdoor(padap, &mps_rplc); in cudbg_collect_tcam_index()
2632 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) { in cudbg_collect_tcam_index()
2641 tcam->rplc_size = padap->params.arch.mps_rplc_size; in cudbg_collect_tcam_index()
2649 struct adapter *padap = pdbg_init->adap; in cudbg_collect_mps_tcam() local
2655 n = padap->params.arch.mps_tcam_size; in cudbg_collect_mps_tcam()
2686 struct adapter *padap = pdbg_init->adap; in cudbg_collect_vpd_data() local
2694 rc = t4_get_raw_vpd_params(padap, &vpd); in cudbg_collect_vpd_data()
2698 rc = t4_get_fw_version(padap, &fw_vers); in cudbg_collect_vpd_data()
2705 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE); in cudbg_collect_vpd_data()
2709 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN, in cudbg_collect_vpd_data()
2713 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE); in cudbg_collect_vpd_data()
2720 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN, in cudbg_collect_vpd_data()
2752 struct adapter *padap = pdbg_init->adap; in cudbg_read_tid() local
2758 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0); in cudbg_read_tid()
2762 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); in cudbg_read_tid()
2766 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); in cudbg_read_tid()
2772 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); in cudbg_read_tid()
2780 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); in cudbg_read_tid()
2787 tid_data->data[i] = t4_read_reg(padap, in cudbg_read_tid()
2838 void cudbg_fill_le_tcam_info(struct adapter *padap, in cudbg_fill_le_tcam_info() argument
2844 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */ in cudbg_fill_le_tcam_info()
2848 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A); in cudbg_fill_le_tcam_info()
2852 if (is_t6(padap->params.chip)) in cudbg_fill_le_tcam_info()
2853 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A); in cudbg_fill_le_tcam_info()
2855 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A); in cudbg_fill_le_tcam_info()
2859 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A); in cudbg_fill_le_tcam_info()
2863 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A); in cudbg_fill_le_tcam_info()
2867 value = t4_read_reg(padap, LE_DB_CONFIG_A); in cudbg_fill_le_tcam_info()
2869 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A); in cudbg_fill_le_tcam_info()
2870 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { in cudbg_fill_le_tcam_info()
2880 if (is_t6(padap->params.chip)) in cudbg_fill_le_tcam_info()
2888 if (is_t6(padap->params.chip)) in cudbg_fill_le_tcam_info()
2896 struct adapter *padap = pdbg_init->adap; in cudbg_collect_le_tcam() local
2904 cudbg_fill_le_tcam_info(padap, &tcam_region); in cudbg_collect_le_tcam()
2929 if (is_t6(padap->params.chip) && in cudbg_collect_le_tcam()
2951 struct adapter *padap = pdbg_init->adap; in cudbg_collect_cctrl() local
2961 t4_read_cong_tbl(padap, (void *)temp_buff.data); in cudbg_collect_cctrl()
2969 struct adapter *padap = pdbg_init->adap; in cudbg_collect_ma_indirect() local
2975 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) in cudbg_collect_ma_indirect()
2993 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data, in cudbg_collect_ma_indirect()
3008 t4_read_indirect(padap, ma_fli->ireg_addr, in cudbg_collect_ma_indirect()
3023 struct adapter *padap = pdbg_init->adap; in cudbg_collect_ulptx_la() local
3045 ulptx_la_buff->rdptr[i] = t4_read_reg(padap, in cudbg_collect_ulptx_la()
3048 ulptx_la_buff->wrptr[i] = t4_read_reg(padap, in cudbg_collect_ulptx_la()
3051 ulptx_la_buff->rddata[i] = t4_read_reg(padap, in cudbg_collect_ulptx_la()
3056 t4_read_reg(padap, in cudbg_collect_ulptx_la()
3061 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1); in cudbg_collect_ulptx_la()
3063 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A); in cudbg_collect_ulptx_la()
3065 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A); in cudbg_collect_ulptx_la()
3067 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A); in cudbg_collect_ulptx_la()
3069 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A); in cudbg_collect_ulptx_la()
3071 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A); in cudbg_collect_ulptx_la()
3073 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A); in cudbg_collect_ulptx_la()
3075 t4_read_reg(padap, PM_RX_BASE_ADDR); in cudbg_collect_ulptx_la()
3085 struct adapter *padap = pdbg_init->adap; in cudbg_collect_up_cim_indirect() local
3093 if (is_t5(padap->params.chip)) in cudbg_collect_up_cim_indirect()
3096 else if (is_t6(padap->params.chip)) in cudbg_collect_up_cim_indirect()
3112 if (is_t5(padap->params.chip)) { in cudbg_collect_up_cim_indirect()
3120 } else if (is_t6(padap->params.chip)) { in cudbg_collect_up_cim_indirect()
3149 rc = t4_cim_read(padap, in cudbg_collect_up_cim_indirect()
3166 struct adapter *padap = pdbg_init->adap; in cudbg_collect_pbt_tables() local
3182 rc = t4_cim_read(padap, addr + (i * 4), 1, in cudbg_collect_pbt_tables()
3195 rc = t4_cim_read(padap, addr + (i * 4), 1, in cudbg_collect_pbt_tables()
3207 rc = t4_cim_read(padap, addr + (i * 4), 1, in cudbg_collect_pbt_tables()
3219 rc = t4_cim_read(padap, addr + (i * 4), 1, in cudbg_collect_pbt_tables()
3234 struct adapter *padap = pdbg_init->adap; in cudbg_collect_mbox_log() local
3245 log = padap->mbox_log; in cudbg_collect_mbox_log()
3246 mbox_cmds = padap->mbox_log->size; in cudbg_collect_mbox_log()
3278 struct adapter *padap = pdbg_init->adap; in cudbg_collect_hma_indirect() local
3284 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) in cudbg_collect_hma_indirect()
3302 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data, in cudbg_collect_hma_indirect()
3310 void cudbg_fill_qdesc_num_and_size(const struct adapter *padap, in cudbg_fill_qdesc_num_and_size() argument
3369 struct adapter *padap = pdbg_init->adap; in cudbg_collect_qdesc() local
3374 struct sge *s = &padap->sge; in cudbg_collect_qdesc()
3379 cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size); in cudbg_collect_qdesc()
3437 for (i = 0; i < padap->params.nports; i++) in cudbg_collect_qdesc()
3572 struct adapter *padap = pdbg_init->adap; in cudbg_collect_flash() local
3573 u32 count = padap->params.sf_size, n; in cudbg_collect_flash()
3588 rc = t4_read_flash(padap, addr, n, (u32 *)temp_buff.data, 0); in cudbg_collect_flash()