Lines Matching refs:tw32
618 #define tw32(reg, val) tp->write32(tp, reg, val) macro
999 tw32(TG3PCI_MISC_HOST_CTRL, in tg3_disable_ints()
1012 tw32(TG3PCI_MISC_HOST_CTRL, in tg3_enable_ints()
1029 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1031 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1076 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1435 tw32(MAC_PHYCFG2, val); in tg3_mdio_config_5785()
1441 tw32(MAC_PHYCFG1, val); in tg3_mdio_config_5785()
1454 tw32(MAC_PHYCFG2, val); in tg3_mdio_config_5785()
1467 tw32(MAC_PHYCFG1, val); in tg3_mdio_config_5785()
1488 tw32(MAC_EXT_RGMII_MODE, val); in tg3_mdio_config_5785()
2054 tw32(MAC_MI_STAT, in tg3_adjust_link()
2058 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); in tg3_adjust_link()
2062 tw32(MAC_TX_LENGTHS, in tg3_adjust_link()
2067 tw32(MAC_TX_LENGTHS, in tg3_adjust_link()
2407 tw32(TG3_CPMU_EEE_CTRL, eeectl); in tg3_phy_eee_adjust()
2422 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_eee_adjust()
2442 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_eee_enable()
2667 tw32(TG3_CPMU_CTRL, in tg3_phy_reset()
2679 tw32(TG3_CPMU_CTRL, cpmuctrl); in tg3_phy_reset()
2808 tw32(TG3_CPMU_DRV_STATUS, status); in tg3_set_function_status()
3074 tw32(SG_DIG_CTRL, sg_dig_ctrl); in tg3_power_down_phy()
3075 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); in tg3_power_down_phy()
3141 tw32(NVRAM_SWARB, SWARB_REQ_SET1); in tg3_nvram_lock()
3148 tw32(NVRAM_SWARB, SWARB_REQ_CLR1); in tg3_nvram_lock()
3174 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); in tg3_enable_nvram_access()
3184 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); in tg3_disable_nvram_access()
3200 tw32(GRC_EEPROM_ADDR, in tg3_nvram_read_using_eeprom()
3234 tw32(NVRAM_CMD, nvram_cmd); in tg3_nvram_exec_cmd()
3303 tw32(NVRAM_ADDR, offset); in tg3_nvram_read()
3347 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); in tg3_nvram_write_block_using_eeprom()
3350 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); in tg3_nvram_write_block_using_eeprom()
3354 tw32(GRC_EEPROM_ADDR, val | in tg3_nvram_write_block_using_eeprom()
3428 tw32(NVRAM_ADDR, phy_addr); in tg3_nvram_write_block_unbuffered()
3447 tw32(NVRAM_WRDATA, be32_to_cpu(data)); in tg3_nvram_write_block_unbuffered()
3449 tw32(NVRAM_ADDR, phy_addr + j); in tg3_nvram_write_block_unbuffered()
3486 tw32(NVRAM_WRDATA, be32_to_cpu(data)); in tg3_nvram_write_block_buffered()
3505 tw32(NVRAM_ADDR, phy_addr); in tg3_nvram_write_block_buffered()
3552 tw32(NVRAM_WRITE1, 0x406); in tg3_nvram_write_block()
3555 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); in tg3_nvram_write_block()
3566 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); in tg3_nvram_write_block()
3592 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu()
3593 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); in tg3_pause_cpu()
3608 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); in tg3_rxcpu_pause()
3624 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_resume_cpu()
3644 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_halt_cpu()
3668 tw32(NVRAM_SWARB, SWARB_REQ_CLR0); in tg3_halt_cpu()
3733 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_load_firmware_cpu()
3734 tw32(cpu_base + CPU_MODE, in tg3_load_firmware_cpu()
3771 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu_and_set_pc()
3777 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu_and_set_pc()
3778 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); in tg3_pause_cpu_and_set_pc()
3960 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high); in __tg3_set_one_mac_addr()
3961 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low); in __tg3_set_one_mac_addr()
3964 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high); in __tg3_set_one_mac_addr()
3965 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low); in __tg3_set_one_mac_addr()
3994 tw32(MAC_TX_BACKOFF_SEED, addr_high); in __tg3_set_mac_addr()
4039 tw32(TG3PCI_MISC_HOST_CTRL, in tg3_power_down_prepare()
4112 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); in tg3_power_down_prepare()
4169 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4255 tw32(0x7d00, val); in tg3_power_down_prepare()
4354 tw32(TG3_CPMU_EEE_MODE, in tg3_phy_autoneg_cfg()
4732 tw32(MAC_EVENT, 0); in tg3_clear_mac_status()
5022 tw32(MAC_LED_CTRL, led_ctrl); in tg3_setup_copper_phy()
5234 tw32(MAC_TX_AUTO_NEG, 0); in tg3_fiber_aneg_smachine()
5263 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5278 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5799 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
6094 tw32(GRC_MISC_CFG, val); in tg3_setup_phy()
6107 tw32(MAC_TX_LENGTHS, val | in tg3_setup_phy()
6110 tw32(MAC_TX_LENGTHS, val | in tg3_setup_phy()
6115 tw32(HOSTCC_STAT_COAL_TICKS, in tg3_setup_phy()
6118 tw32(HOSTCC_STAT_COAL_TICKS, 0); in tg3_setup_phy()
6129 tw32(PCIE_PWR_MGMT_THRESH, val); in tg3_setup_phy()
6153 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP); in tg3_refclk_write()
6154 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff); in tg3_refclk_write()
6155 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32); in tg3_refclk_write()
6214 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, in tg3_ptp_adjfreq()
6218 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0); in tg3_ptp_adjfreq()
6308 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff)); in tg3_ptp_enable()
6309 tw32(TG3_EAV_WATCHDOG0_MSB, in tg3_ptp_enable()
6313 tw32(TG3_EAV_REF_CLCK_CTL, in tg3_ptp_enable()
6316 tw32(TG3_EAV_WATCHDOG0_MSB, 0); in tg3_ptp_enable()
6317 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl); in tg3_ptp_enable()
7271 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
8191 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8282 tw32(MAC_MODE, mac_mode); in tg3_phy_lpbk_set()
8931 tw32(FTQ_RESET, 0xffffffff); in tg3_abort_hw()
8932 tw32(FTQ_RESET, 0x00000000); in tg3_abort_hw()
9009 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); in tg3_restore_pci_state()
9021 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val | in tg3_override_clk()
9027 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN); in tg3_override_clk()
9042 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, in tg3_restore_clk()
9049 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); in tg3_restore_clk()
9086 tw32(GRC_FASTBOOT_PC, 0); in tg3_chip_reset()
9125 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); in tg3_chip_reset()
9137 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); in tg3_chip_reset()
9140 tw32(GRC_MISC_CFG, (1 << 29)); in tg3_chip_reset()
9146 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
9147 tw32(GRC_VCPU_EXT_CTRL, in tg3_chip_reset()
9162 tw32(GRC_MISC_CFG, val); in tg3_chip_reset()
9234 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); in tg3_chip_reset()
9238 tw32(0x5000, 0x400); in tg3_chip_reset()
9255 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9260 tw32(0xc4, val | (1 << 15)); in tg3_chip_reset()
9268 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9293 tw32(0x7c00, val | (1 << 25)); in tg3_chip_reset()
9303 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val | in tg3_chip_reset()
9431 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9432 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9433 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9435 tw32(HOSTCC_TXCOL_TICKS, 0); in tg3_coal_tx_init()
9436 tw32(HOSTCC_TXMAX_FRAMES, 0); in tg3_coal_tx_init()
9437 tw32(HOSTCC_TXCOAL_MAXF_INT, 0); in tg3_coal_tx_init()
9443 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9445 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9447 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9452 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9453 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9454 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9464 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9465 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9466 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9469 tw32(HOSTCC_RXCOL_TICKS, 0); in tg3_coal_rx_init()
9470 tw32(HOSTCC_RXMAX_FRAMES, 0); in tg3_coal_rx_init()
9471 tw32(HOSTCC_RXCOAL_MAXF_INT, 0); in tg3_coal_rx_init()
9478 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9480 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9482 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9486 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9487 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9488 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9500 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9501 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9506 tw32(HOSTCC_STAT_COAL_TICKS, val); in __tg3_set_coalesce()
9647 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_rings_reset()
9649 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
9656 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); in tg3_rings_reset()
9657 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); in tg3_rings_reset()
9688 tw32(RCVBDI_STD_THRESH, val); in tg3_setup_rxbd_thresholds()
9691 tw32(STD_REPLENISH_LWM, bdcache_maxcnt); in tg3_setup_rxbd_thresholds()
9701 tw32(RCVBDI_JUMBO_THRESH, val); in tg3_setup_rxbd_thresholds()
9704 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); in tg3_setup_rxbd_thresholds()
9734 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9735 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9736 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9737 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9781 tw32(MAC_HASH_REG_0, mc_filter[0]); in __tg3_set_rx_mode()
9782 tw32(MAC_HASH_REG_1, mc_filter[1]); in __tg3_set_rx_mode()
9783 tw32(MAC_HASH_REG_2, mc_filter[2]); in __tg3_set_rx_mode()
9784 tw32(MAC_HASH_REG_3, mc_filter[3]); in __tg3_set_rx_mode()
9850 tw32(reg, val); in tg3_rss_write_indir_tbl()
9902 tw32(TG3_CPMU_CTRL, val); in tg3_reset_hw()
9907 tw32(TG3_CPMU_LSPD_10MB_CLK, val); in tg3_reset_hw()
9912 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); in tg3_reset_hw()
9917 tw32(TG3_CPMU_HST_ACC, val); in tg3_reset_hw()
9924 tw32(PCIE_PWR_MGMT_THRESH, val); in tg3_reset_hw()
9927 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); in tg3_reset_hw()
9929 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); in tg3_reset_hw()
9932 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); in tg3_reset_hw()
9940 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); in tg3_reset_hw()
9943 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw()
9946 tw32(GRC_MODE, grc_mode); in tg3_reset_hw()
9955 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); in tg3_reset_hw()
9959 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw()
9962 tw32(GRC_MODE, grc_mode); in tg3_reset_hw()
9971 tw32(TG3_CPMU_PADRNG_CTL, val); in tg3_reset_hw()
9977 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); in tg3_reset_hw()
9982 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
9985 tw32(GRC_MODE, grc_mode); in tg3_reset_hw()
9991 tw32(TG3_CPMU_LSPD_10MB_CLK, val); in tg3_reset_hw()
10009 tw32(TG3PCI_PCISTATE, val); in tg3_reset_hw()
10020 tw32(TG3PCI_PCISTATE, val); in tg3_reset_hw()
10027 tw32(TG3PCI_MSI_DATA, val); in tg3_reset_hw()
10048 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10054 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10073 tw32(TG3_RX_PTP_CTL, in tg3_reset_hw()
10079 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10088 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048); in tg3_reset_hw()
10095 tw32(GRC_MISC_CFG, val); in tg3_reset_hw()
10101 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); in tg3_reset_hw()
10103 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); in tg3_reset_hw()
10105 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); in tg3_reset_hw()
10106 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); in tg3_reset_hw()
10107 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); in tg3_reset_hw()
10113 tw32(BUFMGR_MB_POOL_ADDR, in tg3_reset_hw()
10115 tw32(BUFMGR_MB_POOL_SIZE, in tg3_reset_hw()
10120 tw32(BUFMGR_MB_RDMA_LOW_WATER, in tg3_reset_hw()
10122 tw32(BUFMGR_MB_MACRX_LOW_WATER, in tg3_reset_hw()
10124 tw32(BUFMGR_MB_HIGH_WATER, in tg3_reset_hw()
10127 tw32(BUFMGR_MB_RDMA_LOW_WATER, in tg3_reset_hw()
10129 tw32(BUFMGR_MB_MACRX_LOW_WATER, in tg3_reset_hw()
10131 tw32(BUFMGR_MB_HIGH_WATER, in tg3_reset_hw()
10134 tw32(BUFMGR_DMA_LOW_WATER, in tg3_reset_hw()
10136 tw32(BUFMGR_DMA_HIGH_WATER, in tg3_reset_hw()
10147 tw32(BUFMGR_MODE, val); in tg3_reset_hw()
10159 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10180 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_reset_hw()
10182 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, in tg3_reset_hw()
10190 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, in tg3_reset_hw()
10200 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_reset_hw()
10202 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10206 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, in tg3_reset_hw()
10211 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, in tg3_reset_hw()
10214 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, in tg3_reset_hw()
10227 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); in tg3_reset_hw()
10242 tw32(MAC_RX_MTU_SIZE, in tg3_reset_hw()
10258 tw32(MAC_TX_LENGTHS, val); in tg3_reset_hw()
10261 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); in tg3_reset_hw()
10262 tw32(RCVLPC_CONFIG, 0x0181); in tg3_reset_hw()
10341 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); in tg3_reset_hw()
10355 tw32(tgtreg, val | in tg3_reset_hw()
10364 tw32(RCVLPC_STATS_ENABLE, val); in tg3_reset_hw()
10369 tw32(RCVLPC_STATS_ENABLE, val); in tg3_reset_hw()
10371 tw32(RCVLPC_STATS_ENABLE, 0xffffff); in tg3_reset_hw()
10373 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); in tg3_reset_hw()
10374 tw32(SNDDATAI_STATSENAB, 0xffffff); in tg3_reset_hw()
10375 tw32(SNDDATAI_STATSCTRL, in tg3_reset_hw()
10380 tw32(HOSTCC_MODE, 0); in tg3_reset_hw()
10394 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, in tg3_reset_hw()
10396 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10398 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); in tg3_reset_hw()
10400 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); in tg3_reset_hw()
10411 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10413 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); in tg3_reset_hw()
10414 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); in tg3_reset_hw()
10416 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); in tg3_reset_hw()
10475 tw32(MSGINT_MODE, val); in tg3_reset_hw()
10539 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); in tg3_reset_hw()
10544 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); in tg3_reset_hw()
10546 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); in tg3_reset_hw()
10549 tw32(SNDDATAC_MODE, in tg3_reset_hw()
10552 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); in tg3_reset_hw()
10554 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); in tg3_reset_hw()
10555 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); in tg3_reset_hw()
10559 tw32(RCVDBDI_MODE, val); in tg3_reset_hw()
10560 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); in tg3_reset_hw()
10564 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); in tg3_reset_hw()
10568 tw32(SNDBDI_MODE, val); in tg3_reset_hw()
10569 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); in tg3_reset_hw()
10614 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]); in tg3_reset_hw()
10635 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10637 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); in tg3_reset_hw()
10653 tw32(MAC_SERDES_CFG, val); in tg3_reset_hw()
10656 tw32(MAC_SERDES_CFG, 0x616000); in tg3_reset_hw()
10679 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); in tg3_reset_hw()
10682 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10709 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10710 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10711 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10712 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10722 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); in tg3_reset_hw()
10725 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); in tg3_reset_hw()
10728 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); in tg3_reset_hw()
10731 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); in tg3_reset_hw()
10734 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); in tg3_reset_hw()
10737 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); in tg3_reset_hw()
10740 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); in tg3_reset_hw()
10743 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); in tg3_reset_hw()
10746 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); in tg3_reset_hw()
10749 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); in tg3_reset_hw()
10752 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); in tg3_reset_hw()
10755 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); in tg3_reset_hw()
10792 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_init_hw()
10918 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); in tg3_periodic_fetch_stats()
10947 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); in tg3_periodic_fetch_stats()
11006 tw32(GRC_LOCAL_CTRL, in tg3_timer()
11009 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11297 tw32(MSGINT_MODE, val); in tg3_test_interrupt()
11343 tw32(MSGINT_MODE, val); in tg3_test_interrupt()
11541 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); in tg3_ints_init()
11637 tw32(PCIE_TRANSACTION_CFG, in tg3_start()
12020 tw32(TG3_CPMU_CTRL, cpmu_val & in tg3_get_eeprom()
12084 tw32(TG3_CPMU_CTRL, cpmu_val); in tg3_get_eeprom()
12767 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | in tg3_set_phys_id()
12777 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | in tg3_set_phys_id()
12782 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
13275 tw32(offset, 0); in tg3_test_registers()
13287 tw32(offset, read_mask | write_mask); in tg3_test_registers()
13299 tw32(offset, save_val); in tg3_test_registers()
13308 tw32(offset, save_val); in tg3_test_registers()
13458 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); in tg3_run_loopback()
13675 tw32(i, 0x0); in tg3_test_loopback()
13919 tw32(TG3_RX_PTP_CTL, in tg3_hwtstamp_set()
14393 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_nvram_info()
14499 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_5752_nvram_info()
14575 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_5787_nvram_info()
14693 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_57780_nvram_info()
14766 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_5717_nvram_info()
14883 tw32(NVRAM_CFG1, nvcfg1); in tg3_get_5720_nvram_info()
15407 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); in tg3_issue_otp_command()
15408 tw32(OTP_CTRL, cmd); in tg3_issue_otp_command()
15429 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); in tg3_read_otp_phycfg()
15434 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); in tg3_read_otp_phycfg()
15441 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); in tg3_read_otp_phycfg()
16639 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); in tg3_get_invariants()
16836 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16841 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_get_invariants()
16844 tw32(TG3PCI_REG_BASE_ADDR, 0); in tg3_get_invariants()
17214 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); in tg3_do_test_dma()
17215 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); in tg3_do_test_dma()
17216 tw32(RDMAC_STATUS, 0); in tg3_do_test_dma()
17217 tw32(WDMAC_STATUS, 0); in tg3_do_test_dma()
17219 tw32(BUFMGR_MODE, 0); in tg3_do_test_dma()
17220 tw32(FTQ_RESET, 0); in tg3_do_test_dma()
17263 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); in tg3_do_test_dma()
17265 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); in tg3_do_test_dma()
17381 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17393 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17427 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17458 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17913 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); in tg3_init_one()