Lines Matching refs:tr32
621 #define tr32(reg) tp->read32(tp, reg) macro
667 *val = tr32(TG3PCI_MEM_WIN_DATA); in tg3_read_mem()
1088 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
1143 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1147 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1205 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1208 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1437 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1456 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1469 val = tr32(MAC_EXT_RGMII_MODE); in tg3_mdio_config_5785()
1514 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; in tg3_mdio_init()
1516 is_serdes = tr32(TG3_CPMU_PHY_STRAP) & in tg3_mdio_init()
1623 val = tr32(GRC_RX_CPU_EVENT); in tg3_generate_fw_event()
1653 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1827 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
2379 val = tr32(TG3_CPMU_EEE_MODE); in tg3_eee_pull_config()
2383 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2421 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_adjust()
2441 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_enable()
2639 val = tr32(GRC_MISC_CFG); in tg3_phy_reset()
2665 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_phy_reset()
2684 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_phy_reset()
2798 status = tr32(TG3_CPMU_DRV_STATUS); in tg3_set_function_status()
3069 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_power_down_phy()
3070 u32 serdes_cfg = tr32(MAC_SERDES_CFG); in tg3_power_down_phy()
3082 val = tr32(GRC_MISC_CFG); in tg3_power_down_phy()
3125 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_power_down_phy()
3143 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
3172 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_enable_nvram_access()
3182 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_disable_nvram_access()
3197 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
3208 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
3217 tmp = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
3237 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
3308 *val = tr32(NVRAM_RDDATA); in tg3_nvram_read()
3349 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3361 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3554 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3565 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3594 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3642 u32 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_halt_cpu()
3735 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); in tg3_load_firmware_cpu()
3775 if (tr32(cpu_base + CPU_PC) == pc) in tg3_pause_cpu_and_set_pc()
3818 tr32(RX_CPU_BASE + CPU_PC), in tg3_load_5701_a0_firmware_fix()
3838 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) in tg3_validate_rxcpu_state()
3941 __func__, tr32(cpu_base + CPU_PC), in tg3_load_tso_firmware()
4038 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_power_down_prepare()
4111 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_power_down_prepare()
4252 u32 val = tr32(0x7d00); in tg3_power_down_prepare()
4355 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_autoneg_cfg()
5010 u32 led_ctrl = tr32(MAC_LED_CTRL); in tg3_setup_copper_phy()
5175 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
5176 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
5454 u32 mac_status = tr32(MAC_STATUS); in tg3_init_bcm8002()
5519 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
5524 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
5527 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_setup_fiber_hw_autoneg()
5580 sg_dig_status = tr32(SG_DIG_STATUS); in tg3_setup_fiber_hw_autoneg()
5581 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5625 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5684 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
5690 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_by_hand()
5728 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5757 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5772 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
5778 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5877 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
5946 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
6084 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; in tg3_setup_phy()
6092 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; in tg3_setup_phy()
6101 val |= tr32(MAC_TX_LENGTHS) & in tg3_setup_phy()
6123 val = tr32(PCIE_PWR_MGMT_THRESH); in tg3_setup_phy()
6141 stamp = tr32(TG3_EAV_REF_CLCK_LSB); in tg3_refclk_read()
6143 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32; in tg3_refclk_read()
6151 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write()
6285 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6398 *dst++ = tr32(off + i); in tg3_rd32_loop()
6463 regs[i / sizeof(u32)] = tr32(i); in tg3_dump_state()
6565 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB); in tg3_tx()
6566 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32; in tg3_tx()
6878 tstamp = tr32(TG3_RX_TSTAMP_LSB); in tg3_rx()
6879 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32; in tg3_rx()
7298 val = tr32(HOSTCC_FLOW_ATTN); in tg3_process_error()
7304 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { in tg3_process_error()
7309 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { in tg3_process_error()
7526 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt()
7575 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt_tagged()
7621 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_test_isr()
8846 val = tr32(ofs); in tg3_stop_block()
8860 val = tr32(ofs); in tg3_stop_block()
8917 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
8923 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); in tg3_abort_hw()
9008 val = tr32(MSGINT_MODE); in tg3_restore_pci_state()
9020 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_override_clk()
9041 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_restore_clk()
9048 val = tr32(TG3_CPMU_CLCK_ORIDE); in tg3_restore_clk()
9124 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_chip_reset()
9135 tr32(TG3_PCIE_PHY_TSTCTL) == in tg3_chip_reset()
9146 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
9148 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_chip_reset()
9233 val = tr32(MEMARB_MODE); in tg3_chip_reset()
9258 val = tr32(0xc4); in tg3_chip_reset()
9291 val = tr32(0x7c00); in tg3_chip_reset()
9302 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_chip_reset()
9386 addr0_high = tr32(MAC_ADDR_0_HIGH); in tg3_set_mac_addr()
9387 addr0_low = tr32(MAC_ADDR_0_LOW); in tg3_set_mac_addr()
9388 addr1_high = tr32(MAC_ADDR_1_HIGH); in tg3_set_mac_addr()
9389 addr1_low = tr32(MAC_ADDR_1_LOW); in tg3_set_mac_addr()
9900 val = tr32(TG3_CPMU_CTRL); in tg3_reset_hw()
9904 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9909 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); in tg3_reset_hw()
9914 val = tr32(TG3_CPMU_HST_ACC); in tg3_reset_hw()
9921 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; in tg3_reset_hw()
9926 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; in tg3_reset_hw()
9931 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_reset_hw()
9936 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9942 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw()
9951 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9957 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9969 val = tr32(TG3_CPMU_PADRNG_CTL); in tg3_reset_hw()
9973 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9979 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9988 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
10007 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10016 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10025 val = tr32(TG3PCI_MSI_DATA); in tg3_reset_hw()
10040 val = tr32(TG3PCI_DMA_RW_CTRL) & in tg3_reset_hw()
10087 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK; in tg3_reset_hw()
10092 val = tr32(GRC_MISC_CFG); in tg3_reset_hw()
10149 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
10159 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10254 val |= tr32(MAC_TX_LENGTHS) & in tg3_reset_hw()
10288 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10317 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; in tg3_reset_hw()
10331 val = tr32(tgtreg); in tg3_reset_hw()
10354 val = tr32(tgtreg); in tg3_reset_hw()
10362 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10367 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10382 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
10458 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10469 val = tr32(MSGINT_MODE); in tg3_reset_hw()
10495 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10533 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10537 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_reset_hw()
10600 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10650 val = tr32(MAC_SERDES_CFG); in tg3_reset_hw()
10678 tmp = tr32(SERDES_RX_CTRL); in tg3_reset_hw()
10885 do { u32 __val = tr32(REG); \
10916 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_periodic_fetch_stats()
10944 u32 val = tr32(HOSTCC_FLOW_ATTN); in tg3_periodic_fetch_stats()
10997 tr32(HOSTCC_MODE); in tg3_timer()
11013 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
11032 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11044 u32 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11071 u32 cpmu = tr32(TG3_CPMU_STATUS); in tg3_timer()
11296 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11315 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_test_interrupt()
11342 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11536 u32 msi_mode = tr32(MSGINT_MODE); in tg3_ints_init()
11635 u32 val = tr32(PCIE_TRANSACTION_CFG); in tg3_start()
12017 cpmu_val = tr32(TG3_CPMU_CTRL); in tg3_get_eeprom()
13267 save_val = tr32(offset); in tg3_test_registers()
13277 val = tr32(offset); in tg3_test_registers()
13289 val = tr32(offset); in tg3_test_registers()
13705 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_test_loopback()
14388 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_nvram_info()
14466 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5752_nvram_info()
14507 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5755_nvram_info()
14563 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5787_nvram_info()
14601 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5761_nvram_info()
14641 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14683 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_57780_nvram_info()
14756 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5717_nvram_info()
14834 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5720_nvram_info()
14854 nv_status = tr32(NVRAM_AUTOSENSE_STATUS); in tg3_get_5720_nvram_info()
15014 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
15164 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
15168 val = tr32(VCPU_CFGSHDW); in tg3_get_eeprom_hw_cfg()
15412 val = tr32(OTP_STATUS); in tg3_issue_otp_command()
15439 thalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
15446 bhalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
16186 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; in tg3_10_100_only_device()
16638 val = tr32(MEMARB_MODE); in tg3_get_invariants()
16655 val = tr32(TG3_CPMU_STATUS); in tg3_get_invariants()
16733 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16825 val = tr32(GRC_MODE); in tg3_get_invariants()
16878 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
16980 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17005 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
17044 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
17045 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
17272 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17274 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17326 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
17561 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
17566 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == in tg3_bus_string()
17849 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { in tg3_init_one()
17910 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
17911 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_init_one()