13100 #define TG3_FL_NOT_5705	0x2  in tg3_test_registers()  macro
13107 		{ MAC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13111 		{ MAC_STATUS, TG3_FL_NOT_5705,  in tg3_test_registers()
13125 		{ MAC_RX_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13139 		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,  in tg3_test_registers()
13141 		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13143 		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,  in tg3_test_registers()
13145 		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,  in tg3_test_registers()
13157 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13161 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13165 		{ HOSTCC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13169 		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13173 		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13177 		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13181 		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13185 		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13187 		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13189 		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13193 		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13197 		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13199 		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13201 		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13223 		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13225 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,  in tg3_test_registers()
13231 		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13249 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))  in tg3_test_registers()