Lines Matching +full:dp +full:- +full:phy1
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
122 * and dev->tx_timeout() should be called to fix the problem
145 /* Do not place this n-ring entries value into the tp struct itself,
149 * replace things like '% foo' with '& (foo - 1)'.
153 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
163 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
200 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
206 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
230 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
470 writel(val, tp->regs + off); in tg3_write32()
475 return readl(tp->regs + off); in tg3_read32()
480 writel(val, tp->aperegs + off); in tg3_ape_write32()
485 return readl(tp->aperegs + off); in tg3_ape_read32()
492 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
495 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
500 writel(val, tp->regs + off); in tg3_write_flush_reg32()
501 readl(tp->regs + off); in tg3_write_flush_reg32()
509 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
512 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
531 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
534 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
551 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
554 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
566 /* Non-posted methods */ in _tw32_flush()
567 tp->write32(tp, off, val); in _tw32_flush()
573 tp->read32(tp, off); in _tw32_flush()
584 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
588 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
593 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
604 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
609 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
612 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
614 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
618 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tr32(reg) tp->read32(tp, reg)
631 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
645 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
658 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
672 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
695 if (!tp->pci_fn) in tg3_ape_lock_init()
698 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
721 if (!tp->pci_fn) in tg3_ape_lock()
724 bit = 1 << tp->pci_fn; in tg3_ape_lock()
733 return -EINVAL; in tg3_ape_lock()
753 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
762 ret = -EBUSY; in tg3_ape_lock()
782 if (!tp->pci_fn) in tg3_ape_unlock()
785 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
811 return -EBUSY; in tg3_ape_event_lock()
820 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
823 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
854 return -ENODEV; in tg3_ape_scratchpad_read()
858 return -EAGAIN; in tg3_ape_scratchpad_read()
870 len -= length; in tg3_ape_scratchpad_read()
874 return -EAGAIN; in tg3_ape_scratchpad_read()
895 return -EAGAIN; in tg3_ape_scratchpad_read()
897 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
915 return -EAGAIN; in tg3_ape_send_event()
919 return -EAGAIN; in tg3_ape_send_event()
945 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
962 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
988 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
991 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
992 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1000 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1001 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1002 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1009 tp->irq_sync = 0; in tg3_enable_ints()
1013 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1015 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1016 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1017 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1019 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1023 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1028 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1029 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1031 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1033 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1038 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1039 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1044 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1049 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1053 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1054 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1067 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1069 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1076 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1077 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1094 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1122 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1124 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1128 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1150 loops -= 1; in __tg3_readphy()
1153 ret = -EBUSY; in __tg3_readphy()
1159 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1160 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1164 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1171 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1185 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1187 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1191 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1211 loops -= 1; in __tg3_writephy()
1214 ret = -EBUSY; in __tg3_writephy()
1218 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1219 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1223 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1230 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1360 return -EBUSY; in tg3_bmcr_reset()
1363 while (limit--) { in tg3_bmcr_reset()
1366 return -EBUSY; in tg3_bmcr_reset()
1375 return -EBUSY; in tg3_bmcr_reset()
1382 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1385 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1388 val = -EIO; in tg3_mdio_read()
1390 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1397 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1400 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1403 ret = -EIO; in tg3_mdio_write()
1405 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1415 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1416 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1434 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1493 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1494 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1511 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1519 tp->phy_addr += 7; in tg3_mdio_init()
1523 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1526 tp->phy_addr = addr; in tg3_mdio_init()
1528 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1535 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1536 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1537 return -ENOMEM; in tg3_mdio_init()
1539 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1540 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1541 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1542 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1543 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1544 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1545 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1556 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1558 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1559 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1563 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1565 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1566 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1567 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1568 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1569 return -ENODEV; in tg3_mdio_init()
1572 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1574 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1575 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1579 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1584 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; in tg3_mdio_init()
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; in tg3_mdio_init()
1588 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; in tg3_mdio_init()
1591 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1595 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1596 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1597 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1613 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1614 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1618 /* tp->lock is held. */
1627 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1632 /* tp->lock is held. */
1640 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1641 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1655 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1662 /* tp->lock is held. */
1682 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1697 /* tp->lock is held. */
1719 /* tp->lock is held. */
1735 /* tp->lock is held. */
1764 /* tp->lock is held. */
1785 /* tp->lock is held. */
1829 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1830 return -ENODEV; in tg3_poll_fw()
1834 return -ENODEV; in tg3_poll_fw()
1842 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1845 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1862 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1877 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1878 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1881 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1882 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1884 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1886 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1889 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1892 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1895 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1896 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1897 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1902 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1969 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1970 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1973 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1975 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1978 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1983 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1985 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1988 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1990 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1992 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1993 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1996 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1998 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2000 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
2001 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2009 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2011 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2013 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2016 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2018 if (phydev->link) { in tg3_adjust_link()
2022 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2024 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2030 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2034 tp->link_config.flowctrl); in tg3_adjust_link()
2036 if (phydev->pause) in tg3_adjust_link()
2038 if (phydev->asym_pause) in tg3_adjust_link()
2046 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2047 tp->mac_mode = mac_mode; in tg3_adjust_link()
2048 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2053 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2061 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2072 if (phydev->link != tp->old_link || in tg3_adjust_link()
2073 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2074 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2075 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2078 tp->old_link = phydev->link; in tg3_adjust_link()
2079 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2080 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2082 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2092 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2098 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2101 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2102 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2104 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2109 switch (phydev->interface) { in tg3_phy_init()
2112 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2123 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2124 return -EINVAL; in tg3_phy_init()
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2141 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2145 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2146 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2147 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2149 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2159 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2162 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2167 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2168 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2169 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2178 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2181 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2182 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2229 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2232 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2259 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2262 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2300 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2313 if (!tp->phy_otp) in tg3_phy_apply_otp()
2316 otp = tp->phy_otp; in tg3_phy_apply_otp()
2349 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2351 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2363 dest->eee_active = 1; in tg3_eee_pull_config()
2365 dest->eee_active = 0; in tg3_eee_pull_config()
2370 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2375 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2376 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2380 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2383 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2390 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2393 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2395 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2397 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2398 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2399 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2402 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2410 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2411 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2414 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2430 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2449 while (limit--) { in tg3_wait_macro_done()
2458 return -EBUSY; in tg3_wait_macro_done()
2487 return -EBUSY; in tg3_phy_write_and_check_testpat()
2495 return -EBUSY; in tg3_phy_write_and_check_testpat()
2501 return -EBUSY; in tg3_phy_write_and_check_testpat()
2511 return -EBUSY; in tg3_phy_write_and_check_testpat()
2521 return -EBUSY; in tg3_phy_write_and_check_testpat()
2543 return -EBUSY; in tg3_phy_reset_chanpat()
2571 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2592 } while (--retries); in tg3_phy_reset_5703_4_5()
2619 netif_carrier_off(tp->dev); in tg3_carrier_off()
2620 tp->link_up = false; in tg3_carrier_off()
2626 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2627 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2631 * link unless the FORCE argument is non-zero.
2646 return -EBUSY; in tg3_phy_reset()
2648 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2649 netif_carrier_off(tp->dev); in tg3_phy_reset()
2694 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2699 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2705 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2717 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2724 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2727 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2740 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2741 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2744 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2800 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2822 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2847 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2869 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2876 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2877 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2878 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2884 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2902 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2908 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2921 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2927 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2933 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2980 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2983 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3010 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3012 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3028 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3032 if (!tp->pci_fn) in tg3_phy_power_bug()
3037 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3038 !tp->pci_fn) in tg3_phy_power_bug()
3051 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3052 !tp->pci_fn) in tg3_phy_led_bug()
3064 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3067 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3086 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3134 /* tp->lock is held. */
3140 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3149 return -ENODEV; in tg3_nvram_lock()
3152 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3157 /* tp->lock is held. */
3161 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3162 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3163 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3168 /* tp->lock is held. */
3178 /* tp->lock is held. */
3195 return -EINVAL; in tg3_nvram_read_using_eeprom()
3215 return -EBUSY; in tg3_nvram_read_using_eeprom()
3244 return -EBUSY; in tg3_nvram_exec_cmd()
3255 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3257 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3259 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3270 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3273 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3274 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3283 * machine, the 32-bit value will be byteswapped.
3295 return -EINVAL; in tg3_nvram_read()
3368 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3381 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3382 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3388 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3410 len -= size; in tg3_nvram_write_block_unbuffered()
3414 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3456 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3488 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3496 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3499 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3509 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3536 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3573 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3585 /* tp->lock is held. */
3596 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3597 return -EBUSY; in tg3_pause_cpu()
3600 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3603 /* tp->lock is held. */
3615 /* tp->lock is held. */
3621 /* tp->lock is held. */
3628 /* tp->lock is held. */
3634 /* tp->lock is held. */
3661 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3663 return -ENODEV; in tg3_halt_cpu()
3681 * tp->fw->size minus headers. in tg3_fw_data_len()
3691 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3692 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3694 fw_len = tp->fw->size; in tg3_fw_data_len()
3696 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3699 /* tp->lock is held. */
3706 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3709 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3712 return -EINVAL; in tg3_load_firmware_cpu()
3740 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3748 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3752 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3756 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3765 /* tp->lock is held. */
3783 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3786 /* tp->lock is held. */
3792 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3796 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3814 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3816 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3819 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3820 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3845 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3846 return -EBUSY; in tg3_validate_rxcpu_state()
3851 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3853 return -EEXIST; in tg3_validate_rxcpu_state()
3859 /* tp->lock is held. */
3870 if (!tp->fw) in tg3_load_57766_firmware()
3875 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3887 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3888 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3900 /* tp->lock is held. */
3910 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3914 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3918 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3937 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3939 netdev_err(tp->dev, in tg3_load_tso_firmware()
3942 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3943 return -ENODEV; in tg3_load_tso_firmware()
3950 /* tp->lock is held. */
3963 index -= 4; in __tg3_set_one_mac_addr()
3969 /* tp->lock is held. */
3978 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3984 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3987 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3990 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3991 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3992 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
4003 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4004 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4013 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4018 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4035 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4042 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4047 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4048 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4053 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4055 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4057 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4058 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4059 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4061 &tp->link_config.advertising, in tg3_power_down_prepare()
4062 phydev->advertising); in tg3_power_down_prepare()
4086 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4089 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4101 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4102 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4104 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4133 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4135 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4144 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4146 else if (tp->phy_flags & in tg3_power_down_prepare()
4148 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4155 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4169 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4193 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4223 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4239 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4275 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4276 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4313 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4339 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4351 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4362 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4365 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4369 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4371 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4373 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4412 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4413 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4416 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4417 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4423 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4424 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4432 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4433 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4437 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4442 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4443 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4457 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4458 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4469 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4483 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4517 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4518 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4521 err = -EIO; in tg3_phy_pull_config()
4525 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4528 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4531 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4537 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4538 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4547 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4549 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4551 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4557 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4558 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4561 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4569 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4571 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4573 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4576 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4579 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4591 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4597 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4627 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4632 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4633 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4634 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4635 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4650 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4654 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4655 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4665 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4694 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4707 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4714 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4716 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4718 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4719 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4720 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4757 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4767 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4771 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4789 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4791 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4797 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4803 tp->link_up) { in tg3_setup_copper_phy()
4812 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4833 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4836 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4857 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4859 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4864 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4874 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4875 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4877 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4926 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4927 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4929 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4943 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4950 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4951 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4957 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4960 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4969 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4976 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4984 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4985 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4990 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4994 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4996 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4997 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5001 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
5002 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5004 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5013 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5015 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5018 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5026 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5027 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5028 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5032 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5033 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5035 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5041 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5043 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5044 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5048 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5063 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5077 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5078 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5079 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5082 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5151 #define ANEG_FAILED -1
5163 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5164 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5165 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5166 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5167 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5168 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5169 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5170 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5171 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5173 ap->cur_time++; in tg3_fiber_aneg_smachine()
5178 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5179 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5180 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5181 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5183 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5184 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5185 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5189 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5191 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5193 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5195 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5196 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5197 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5198 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5199 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5204 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5207 switch (ap->state) { in tg3_fiber_aneg_smachine()
5209 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5210 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5214 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5215 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5216 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5217 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5218 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5219 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5220 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5221 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5222 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5224 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5226 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5231 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5232 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5233 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5236 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5240 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5244 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5246 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5256 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5257 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5258 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5260 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5262 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5263 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5264 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5265 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5268 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5272 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5273 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5277 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5278 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5280 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5283 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5287 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5288 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5292 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5294 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5295 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5296 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5301 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5314 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5315 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5316 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5317 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5319 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5322 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5324 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5326 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5327 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5329 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5331 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5332 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5333 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5334 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5335 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5336 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5338 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5343 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5344 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5345 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5348 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5353 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5354 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5355 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5364 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5366 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5369 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5374 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5375 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5376 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5379 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5382 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5438 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5476 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5522 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5523 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5529 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5550 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5553 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5560 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5561 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5565 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5576 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5577 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5597 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5602 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5603 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5605 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5606 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5622 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5630 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5632 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5639 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5640 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5654 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5671 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5701 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5704 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5721 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5722 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5723 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5726 tp->link_up && in tg3_setup_fiber_phy()
5743 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5744 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5745 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5748 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5756 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5764 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5766 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5781 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5782 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5783 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5786 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5791 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5792 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5797 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5798 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5799 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5805 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5807 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5808 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5832 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5835 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5843 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5846 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5855 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5863 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5864 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5872 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5885 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5886 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5888 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5897 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5898 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5906 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5907 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5917 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5927 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5951 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5979 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5993 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5994 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5995 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5997 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
6002 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
6003 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6011 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6013 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6017 if (!tp->link_up && in tg3_serdes_parallel_detect()
6018 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6023 u32 phy1, phy2; in tg3_serdes_parallel_detect() local
6027 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6035 if ((phy1 & 0x10) && !(phy2 & 0x20)) { in tg3_serdes_parallel_detect()
6044 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6047 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6048 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6049 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6063 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6074 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6076 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6105 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6106 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6114 if (tp->link_up) { in tg3_setup_phy()
6116 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6124 if (!tp->link_up) in tg3_setup_phy()
6126 tp->pwrmgmt_thresh; in tg3_setup_phy()
6135 /* tp->lock must be held */
6148 /* tp->lock must be held */
6165 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6170 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6175 if (tp->ptp_clock) in tg3_get_ts_info()
6176 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6178 info->phc_index = -1; in tg3_get_ts_info()
6180 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6182 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6197 ppb = -ppb; in tg3_ptp_adjfreq()
6230 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6244 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6262 tp->ptp_adjust = 0; in tg3_ptp_settime()
6275 switch (rq->type) { in tg3_ptp_enable()
6278 if (rq->perout.flags) in tg3_ptp_enable()
6279 return -EOPNOTSUPP; in tg3_ptp_enable()
6281 if (rq->perout.index != 0) in tg3_ptp_enable()
6282 return -EINVAL; in tg3_ptp_enable()
6291 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6292 rq->perout.start.nsec; in tg3_ptp_enable()
6294 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6295 netdev_warn(tp->dev, in tg3_ptp_enable()
6296 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6297 rval = -EINVAL; in tg3_ptp_enable()
6302 netdev_warn(tp->dev, in tg3_ptp_enable()
6304 rval = -EINVAL; in tg3_ptp_enable()
6328 return -EOPNOTSUPP; in tg3_ptp_enable()
6351 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6352 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6355 /* tp->lock must be held */
6363 tp->ptp_adjust = 0; in tg3_ptp_init()
6364 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6367 /* tp->lock must be held */
6373 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6374 tp->ptp_adjust = 0; in tg3_ptp_resume()
6379 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6382 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6383 tp->ptp_clock = NULL; in tg3_ptp_fini()
6384 tp->ptp_adjust = 0; in tg3_ptp_fini()
6389 return tp->irq_sync; in tg3_irq_sync()
6472 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6479 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6480 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6483 netdev_err(tp->dev, in tg3_dump_state()
6486 tnapi->hw_status->status, in tg3_dump_state()
6487 tnapi->hw_status->status_tag, in tg3_dump_state()
6488 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6489 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6490 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6491 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6492 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6494 netdev_err(tp->dev, in tg3_dump_state()
6497 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6498 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6499 tnapi->rx_rcb_ptr, in tg3_dump_state()
6500 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6501 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6502 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6503 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6507 /* This is called whenever we suspect that the system chipset is re-
6516 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6518 netdev_warn(tp->dev, in tg3_tx_recover()
6519 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6531 return tnapi->tx_pending - in tg3_tx_avail()
6532 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6541 struct tg3 *tp = tnapi->tp; in tg3_tx()
6542 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6543 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6545 int index = tnapi - tp->napi; in tg3_tx()
6549 index--; in tg3_tx()
6551 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6554 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6555 struct sk_buff *skb = ri->skb; in tg3_tx()
6563 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6573 pci_unmap_single(tp->pdev, in tg3_tx()
6578 ri->skb = NULL; in tg3_tx()
6580 while (ri->fragmented) { in tg3_tx()
6581 ri->fragmented = false; in tg3_tx()
6583 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6588 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6589 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6590 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6593 pci_unmap_page(tp->pdev, in tg3_tx()
6595 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6598 while (ri->fragmented) { in tg3_tx()
6599 ri->fragmented = false; in tg3_tx()
6601 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6608 bytes_compl += skb->len; in tg3_tx()
6620 tnapi->tx_cons = sw_idx; in tg3_tx()
6652 if (!ri->data) in tg3_rx_data_free()
6655 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), in tg3_rx_data_free()
6657 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6658 ri->data = NULL; in tg3_rx_data_free()
6685 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6686 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6687 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6688 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6692 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6693 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6694 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6699 return -EINVAL; in tg3_alloc_rx_data()
6718 return -ENOMEM; in tg3_alloc_rx_data()
6720 mapping = pci_map_single(tp->pdev, in tg3_alloc_rx_data()
6724 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { in tg3_alloc_rx_data()
6726 return -EIO; in tg3_alloc_rx_data()
6729 map->data = data; in tg3_alloc_rx_data()
6732 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6733 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6747 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6750 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6755 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6756 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6757 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6758 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6759 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6763 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6764 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6765 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6766 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6767 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6774 dest_map->data = src_map->data; in tg3_recycle_rx()
6777 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6778 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6785 src_map->data = NULL; in tg3_recycle_rx()
6800 * it is first placed into the on-chip ram. When the packet's length
6808 * rings, then cache lines never move beyond shared-modified state.
6814 struct tg3 *tp = tnapi->tp; in tg3_rx()
6817 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6820 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6822 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6830 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6831 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6834 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6842 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6843 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6845 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6847 data = ri->data; in tg3_rx()
6851 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6853 data = ri->data; in tg3_rx()
6860 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6866 tp->rx_dropped++; in tg3_rx()
6871 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6874 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6876 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6891 pci_unmap_single(tp->pdev, dma_addr, skb_size, in tg3_rx()
6899 ri->data = NULL; in tg3_rx()
6911 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6917 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6918 memcpy(skb->data, in tg3_rx()
6921 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6929 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6930 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6931 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6933 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6937 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6939 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6940 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6941 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6946 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6947 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6949 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6951 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6954 budget--; in tg3_rx()
6959 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6960 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6961 tp->rx_std_ring_mask; in tg3_rx()
6963 tpr->rx_std_prod_idx); in tg3_rx()
6969 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6973 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6979 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
6980 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
6988 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6989 tp->rx_std_ring_mask; in tg3_rx()
6991 tpr->rx_std_prod_idx); in tg3_rx()
6994 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
6995 tp->rx_jmb_ring_mask; in tg3_rx()
6997 tpr->rx_jmb_prod_idx); in tg3_rx()
7005 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7006 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7008 if (tnapi != &tp->napi[1]) { in tg3_rx()
7009 tp->rx_refill = true; in tg3_rx()
7010 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7021 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7023 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7024 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7025 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7026 spin_lock(&tp->lock); in tg3_poll_link()
7036 spin_unlock(&tp->lock); in tg3_poll_link()
7049 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7056 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7059 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7060 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7062 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7063 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7066 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7068 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7069 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7072 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7073 cpycnt = i - di; in tg3_rx_prodring_xfer()
7074 err = -ENOSPC; in tg3_rx_prodring_xfer()
7088 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7089 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7094 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7095 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7096 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7097 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7100 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7101 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7102 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7103 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7107 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7114 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7117 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7118 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7120 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7121 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7124 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7126 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7127 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7130 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7131 cpycnt = i - di; in tg3_rx_prodring_xfer()
7132 err = -ENOSPC; in tg3_rx_prodring_xfer()
7146 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7147 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7152 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7153 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7154 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7155 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7158 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7159 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7160 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7161 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7169 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7172 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7178 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7183 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7185 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7186 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7188 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7189 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7191 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7192 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7194 tp->rx_refill = false; in tg3_poll_work()
7195 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7197 &tp->napi[i].prodring); in tg3_poll_work()
7201 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7203 dpr->rx_std_prod_idx); in tg3_poll_work()
7205 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7207 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7210 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7218 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7219 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7224 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7225 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7232 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7234 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7245 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7249 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7250 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7254 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7255 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7260 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7265 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7270 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7271 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7273 tnapi->coal_now); in tg3_poll_msix()
7300 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7305 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7310 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7326 struct tg3 *tp = tnapi->tp; in tg3_poll()
7328 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7331 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7345 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7349 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7350 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7353 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7376 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7377 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7384 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7385 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7392 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); in tg3_napi_init()
7393 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7394 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); in tg3_napi_init()
7401 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7402 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7407 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7409 netif_carrier_off(tp->dev); in tg3_netif_stop()
7410 netif_tx_disable(tp->dev); in tg3_netif_stop()
7413 /* tp->lock must be held */
7422 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7424 if (tp->link_up) in tg3_netif_start()
7425 netif_carrier_on(tp->dev); in tg3_netif_start()
7428 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7433 __releases(tp->lock) in tg3_irq_quiesce()
7434 __acquires(tp->lock) in tg3_irq_quiesce()
7438 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7440 tp->irq_sync = 1; in tg3_irq_quiesce()
7443 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7445 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7446 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7448 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7452 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7458 spin_lock_bh(&tp->lock); in tg3_full_lock()
7465 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7468 /* One-shot MSI handler - Chip automatically disables interrupt
7474 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7476 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7477 if (tnapi->rx_rcb) in tg3_msi_1shot()
7478 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7481 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7486 /* MSI ISR - No need to check for interrupt sharing and no need to
7493 struct tg3 *tp = tnapi->tp; in tg3_msi()
7495 prefetch(tnapi->hw_status); in tg3_msi()
7496 if (tnapi->rx_rcb) in tg3_msi()
7497 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7499 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7500 * chip-internal interrupt pending events. in tg3_msi()
7501 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7502 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7505 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7507 napi_schedule(&tnapi->napi); in tg3_msi()
7515 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7516 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7524 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7533 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7534 * chip-internal interrupt pending events. in tg3_interrupt()
7535 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7536 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7539 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7546 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7548 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7549 napi_schedule(&tnapi->napi); in tg3_interrupt()
7551 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7564 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7565 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7573 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7582 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7583 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7584 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7585 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7588 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7600 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7605 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7607 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7617 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7618 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7620 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7637 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7638 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7676 /* Test for DMA addresses > 40-bit */
7693 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7694 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7695 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7696 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7703 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7718 if (tp->dma_limit) { in tg3_tx_frag_set()
7721 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7722 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7723 len -= tp->dma_limit; in tg3_tx_frag_set()
7727 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7728 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7731 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7733 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7735 *budget -= 1; in tg3_tx_frag_set()
7744 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7746 *budget -= 1; in tg3_tx_frag_set()
7750 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7754 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7766 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7768 skb = txb->skb; in tg3_tx_skb_unmap()
7769 txb->skb = NULL; in tg3_tx_skb_unmap()
7771 pci_unmap_single(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7776 while (txb->fragmented) { in tg3_tx_skb_unmap()
7777 txb->fragmented = false; in tg3_tx_skb_unmap()
7779 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7783 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7786 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7788 pci_unmap_page(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7792 while (txb->fragmented) { in tg3_tx_skb_unmap()
7793 txb->fragmented = false; in tg3_tx_skb_unmap()
7795 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7800 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7806 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7814 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7822 ret = -1; in tigon3_dma_hwbug_workaround()
7825 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, in tigon3_dma_hwbug_workaround()
7828 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
7830 ret = -1; in tigon3_dma_hwbug_workaround()
7836 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7837 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7841 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7843 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7845 ret = -1; in tigon3_dma_hwbug_workaround()
7860 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7871 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7890 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7897 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7912 int i = -1, would_hit_hwbug; in tg3_start_xmit()
7923 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7930 * and TX reclaim runs via tp->napi.poll inside of a software in tg3_start_xmit()
7934 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
7945 entry = tnapi->tx_prod; in tg3_start_xmit()
7948 mss = skb_shinfo(skb)->gso_size; in tg3_start_xmit()
7958 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; in tg3_start_xmit()
7963 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
7964 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
7977 ip_csum = iph->check; in tg3_start_xmit()
7978 ip_tot_len = iph->tot_len; in tg3_start_xmit()
7979 iph->check = 0; in tg3_start_xmit()
7980 iph->tot_len = htons(mss + hdr_len); in tg3_start_xmit()
7987 tcp_csum = tcph->check; in tg3_start_xmit()
7992 tcph->check = 0; in tg3_start_xmit()
7995 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in tg3_start_xmit()
8008 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8011 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8015 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8018 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8022 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in tg3_start_xmit()
8026 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
8027 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
8036 !mss && skb->len > VLAN_ETH_FRAME_LEN) in tg3_start_xmit()
8044 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in tg3_start_xmit()
8046 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in tg3_start_xmit()
8052 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); in tg3_start_xmit()
8053 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
8057 tnapi->tx_buffers[entry].skb = skb; in tg3_start_xmit()
8058 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in tg3_start_xmit()
8066 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in tg3_start_xmit()
8069 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
8080 last = skb_shinfo(skb)->nr_frags - 1; in tg3_start_xmit()
8082 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_start_xmit()
8085 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8088 tnapi->tx_buffers[entry].skb = NULL; in tg3_start_xmit()
8089 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in tg3_start_xmit()
8091 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8106 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in tg3_start_xmit()
8113 iph->check = ip_csum; in tg3_start_xmit()
8114 iph->tot_len = ip_tot_len; in tg3_start_xmit()
8116 tcph->check = tcp_csum; in tg3_start_xmit()
8123 entry = tnapi->tx_prod; in tg3_start_xmit()
8131 netdev_tx_sent_queue(txq, skb->len); in tg3_start_xmit()
8136 tnapi->tx_prod = entry; in tg3_start_xmit()
8152 tw32_tx_mbox(tnapi->prodmbox, entry); in tg3_start_xmit()
8158 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in tg3_start_xmit()
8159 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in tg3_start_xmit()
8163 tp->tx_dropped++; in tg3_start_xmit()
8170 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8173 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8176 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8178 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8179 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8181 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8183 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8186 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8188 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8191 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8203 return -EIO; in tg3_phy_lpbk_set()
8214 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8224 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8240 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8245 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8256 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8260 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8263 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8271 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8293 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8296 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8298 netif_carrier_on(tp->dev); in tg3_set_loopback()
8299 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8302 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8305 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8309 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8319 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8327 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8340 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8341 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8342 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8343 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8344 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8347 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8348 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8349 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8350 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8358 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8359 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8360 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8363 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8364 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8373 * end up in the driver. tp->{tx,}lock are held and thus
8381 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8382 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8383 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8384 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8386 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8387 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8389 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8390 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8396 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8400 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8402 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8408 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8411 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8412 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8413 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8414 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8419 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8424 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8427 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8430 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8438 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8443 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8446 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8447 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8448 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8450 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8454 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8459 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8462 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8465 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8475 return -ENOMEM; in tg3_rx_prodring_alloc()
8481 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8482 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8483 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8484 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8485 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8486 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8487 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8488 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8490 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8491 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8492 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8493 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8500 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8502 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8503 return -ENOMEM; in tg3_rx_prodring_init()
8505 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8507 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8509 if (!tpr->rx_std) in tg3_rx_prodring_init()
8513 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8515 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8518 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8520 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8522 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8530 return -ENOMEM; in tg3_rx_prodring_init()
8537 * end up in the driver. tp->{tx,}lock is not held and we are not
8544 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8545 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8547 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8549 if (!tnapi->tx_buffers) in tg3_free_rings()
8553 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8559 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8563 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8571 * end up in the driver. tp->{tx,}lock are held and thus
8581 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8582 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8584 tnapi->last_tag = 0; in tg3_init_rings()
8585 tnapi->last_irq_tag = 0; in tg3_init_rings()
8586 tnapi->hw_status->status = 0; in tg3_init_rings()
8587 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8588 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8590 tnapi->tx_prod = 0; in tg3_init_rings()
8591 tnapi->tx_cons = 0; in tg3_init_rings()
8592 if (tnapi->tx_ring) in tg3_init_rings()
8593 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8595 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8596 if (tnapi->rx_rcb) in tg3_init_rings()
8597 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8599 if (tnapi->prodring.rx_std && in tg3_init_rings()
8600 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8602 return -ENOMEM; in tg3_init_rings()
8613 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8614 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8616 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8617 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8618 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8619 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8622 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8623 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8630 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8638 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8639 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8642 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8645 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8647 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8649 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8657 return -ENOMEM; in tg3_mem_tx_acquire()
8664 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8665 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8667 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8669 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8672 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8674 tnapi->rx_rcb, in tg3_mem_rx_release()
8675 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8676 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8684 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8693 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8695 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8705 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8707 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8709 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8717 return -ENOMEM; in tg3_mem_rx_acquire()
8728 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8729 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8731 if (tnapi->hw_status) { in tg3_free_consistent()
8732 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8733 tnapi->hw_status, in tg3_free_consistent()
8734 tnapi->status_mapping); in tg3_free_consistent()
8735 tnapi->hw_status = NULL; in tg3_free_consistent()
8742 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8744 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8746 if (tp->hw_stats) { in tg3_free_consistent()
8747 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8748 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8749 tp->hw_stats = NULL; in tg3_free_consistent()
8761 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8763 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8764 if (!tp->hw_stats) in tg3_alloc_consistent()
8767 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8768 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8771 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8773 &tnapi->status_mapping, in tg3_alloc_consistent()
8775 if (!tnapi->hw_status) in tg3_alloc_consistent()
8778 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8791 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8794 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8797 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8800 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8803 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8805 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8816 return -ENOMEM; in tg3_alloc_consistent()
8822 * clears. tp->lock is held.
8851 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8852 dev_err(&tp->pdev->dev, in tg3_stop_block()
8856 return -ENODEV; in tg3_stop_block()
8866 dev_err(&tp->pdev->dev, in tg3_stop_block()
8869 return -ENODEV; in tg3_stop_block()
8875 /* tp->lock is held. */
8882 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8883 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8884 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8885 err = -ENODEV; in tg3_abort_hw()
8889 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8890 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8908 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8909 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8912 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8913 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8921 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8924 err |= -ENODEV; in tg3_abort_hw()
8938 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8939 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8940 if (tnapi->hw_status) in tg3_abort_hw()
8941 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
8950 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8958 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
8959 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8960 tp->misc_host_ctrl); in tg3_restore_pci_state()
8972 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8974 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8977 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8978 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8979 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8980 tp->pci_lat_timer); in tg3_restore_pci_state()
8983 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
8987 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8990 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9002 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9003 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9005 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9006 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9057 /* tp->lock is held. */
9059 __releases(tp->lock) in tg3_chip_reset()
9060 __acquires(tp->lock) in tg3_chip_reset()
9066 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9067 return -ENODEV; in tg3_chip_reset()
9076 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9094 write_op = tp->write32; in tg3_chip_reset()
9096 tp->write32 = tg3_write32; in tg3_chip_reset()
9105 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9106 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9107 if (tnapi->hw_status) { in tg3_chip_reset()
9108 tnapi->hw_status->status = 0; in tg3_chip_reset()
9109 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9111 tnapi->last_tag = 0; in tg3_chip_reset()
9112 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9118 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9119 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9165 tp->write32 = write_op; in tg3_chip_reset()
9188 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9192 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9203 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9204 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9216 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9219 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9255 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9263 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9265 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9267 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9268 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9271 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9272 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9273 val = tp->mac_mode; in tg3_chip_reset()
9274 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9275 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9276 val = tp->mac_mode; in tg3_chip_reset()
9309 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9320 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9326 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9328 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9339 /* tp->lock is held. */
9356 if (tp->hw_stats) { in tg3_halt()
9358 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9359 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9362 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9375 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9376 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9378 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); in tg3_set_mac_addr()
9396 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9399 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9404 /* tp->lock is held. */
9431 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9432 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9433 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9439 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9443 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9445 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9447 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9451 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9461 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9464 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9465 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9466 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9467 limit--; in tg3_coal_rx_init()
9478 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9480 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9482 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9485 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9498 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9500 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9501 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9503 if (!tp->link_up) in __tg3_set_coalesce()
9510 /* tp->lock is held. */
9532 /* tp->lock is held. */
9541 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9542 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9544 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9547 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9553 /* tp->lock is held. */
9576 /* tp->lock is held. */
9585 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9586 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9588 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9591 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9592 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9597 /* tp->lock is held. */
9602 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9609 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9610 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9611 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9612 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9616 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9617 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9618 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9620 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9621 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9622 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9623 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9624 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9625 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9628 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9630 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9631 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9632 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9633 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9636 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9644 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9648 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9650 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9654 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9655 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9661 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9684 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9685 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9698 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9745 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9756 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9759 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9774 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9789 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9795 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9801 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9802 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9813 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9823 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9824 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9830 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9835 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9844 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9848 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9863 /* tp->lock is held. */
9868 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9879 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9880 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9883 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9887 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10001 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10002 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10048 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10054 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10057 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10061 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10063 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10064 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10066 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10069 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10072 if (tp->rxptpctl) in tg3_reset_hw()
10074 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10079 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10085 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10086 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10111 fw_len = tp->fw_len; in tg3_reset_hw()
10112 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10116 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10119 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10121 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10123 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10125 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10128 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10130 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10132 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10135 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10137 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10154 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10155 return -ENODEV; in tg3_reset_hw()
10181 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10183 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10201 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10203 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10229 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10230 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10232 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10233 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10234 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10243 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10298 tp->dma_limit = 0; in tg3_reset_hw()
10299 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10301 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10387 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10395 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10397 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10411 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10418 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10419 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10425 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10429 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10431 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10433 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10434 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10437 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10457 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10458 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10462 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10465 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10471 if (tp->irq_cnt > 1) in tg3_reset_hw()
10514 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10523 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10590 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10594 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10599 tp->tx_mode &= ~val; in tg3_reset_hw()
10600 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10603 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10617 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10619 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10622 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10625 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10632 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10635 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10638 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10642 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10645 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10647 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10649 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10669 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10670 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10674 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10680 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10681 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10682 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10686 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10687 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10693 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10694 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10706 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10719 limit -= 4; in tg3_reset_hw()
10779 * packet processing. Invoked with tp->lock held.
10806 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10807 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10820 spin_lock_bh(&tp->lock); in tg3_show_temp()
10821 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10823 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10845 if (tp->hwmon_dev) { in tg3_hwmon_close()
10846 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10847 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10855 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10871 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10873 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10874 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10875 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10886 (PSTAT)->low += __val; \
10887 if ((PSTAT)->low < __val) \
10888 (PSTAT)->high += 1; \
10893 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10895 if (!tp->link_up) in tg3_periodic_fetch_stats()
10898 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10899 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10900 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10901 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10902 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10903 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10904 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10905 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10906 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10907 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10908 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10909 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10910 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10912 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10913 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
10922 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10923 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
10924 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
10925 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
10926 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
10927 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
10928 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
10929 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10930 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10931 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
10932 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
10933 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
10934 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
10935 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
10937 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
10942 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
10948 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
10949 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
10950 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
10952 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
10954 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
10961 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10962 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10965 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
10966 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
10967 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
10968 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
10974 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
10975 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
10976 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
10984 spin_lock(&tp->lock); in tg3_timer()
10986 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10987 spin_unlock(&tp->lock); in tg3_timer()
11001 /* All of this garbage is because when using non-tagged in tg3_timer()
11005 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11007 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11009 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11014 spin_unlock(&tp->lock); in tg3_timer()
11021 if (!--tp->timer_counter) { in tg3_timer()
11025 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11035 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11047 if (tp->link_up && in tg3_timer()
11051 if (!tp->link_up && in tg3_timer()
11057 if (!tp->serdes_counter) { in tg3_timer()
11059 (tp->mac_mode & in tg3_timer()
11062 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11067 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11075 if (link_up != tp->link_up) in tg3_timer()
11079 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11099 if (!--tp->asf_counter) { in tg3_timer()
11111 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11117 spin_unlock(&tp->lock); in tg3_timer()
11120 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11121 add_timer(&tp->timer); in tg3_timer()
11129 tp->timer_offset = HZ; in tg3_timer_init()
11131 tp->timer_offset = HZ / 10; in tg3_timer_init()
11133 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11135 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11136 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11139 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11144 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11145 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11147 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11148 add_timer(&tp->timer); in tg3_timer_start()
11153 del_timer_sync(&tp->timer); in tg3_timer_stop()
11156 /* Restart hardware after configuration changes, self-test, etc.
11157 * Invoked with tp->lock held.
11160 __releases(tp->lock) in tg3_restart_hw()
11161 __acquires(tp->lock) in tg3_restart_hw()
11167 netdev_err(tp->dev, in tg3_restart_hw()
11168 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11172 tp->irq_sync = 0; in tg3_restart_hw()
11174 dev_close(tp->dev); in tg3_restart_hw()
11188 if (!netif_running(tp->dev)) { in tg3_reset_task()
11204 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11205 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11214 tp->irq_sync = 0; in tg3_reset_task()
11220 dev_close(tp->dev); in tg3_reset_task()
11241 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11243 if (tp->irq_cnt == 1) in tg3_request_irq()
11244 name = tp->dev->name; in tg3_request_irq()
11246 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11247 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11249 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11250 else if (tnapi->tx_buffers) in tg3_request_irq()
11252 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11253 else if (tnapi->rx_rcb) in tg3_request_irq()
11255 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11258 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11259 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11274 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11279 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11280 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11285 return -ENODEV; in tg3_test_interrupt()
11289 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11300 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11301 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11305 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11308 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11309 tnapi->coal_now); in tg3_test_interrupt()
11314 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11324 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11325 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11332 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11348 return -EIO; in tg3_test_interrupt()
11365 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11366 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11371 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11377 if (err != -EIO) in tg3_test_msi()
11381 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11385 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11387 pci_disable_msi(tp->pdev); in tg3_test_msi()
11390 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11407 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11416 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11417 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11418 tp->fw_needed); in tg3_request_firmware()
11419 return -ENOENT; in tg3_request_firmware()
11422 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11429 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11430 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11431 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11432 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11433 release_firmware(tp->fw); in tg3_request_firmware()
11434 tp->fw = NULL; in tg3_request_firmware()
11435 return -EINVAL; in tg3_request_firmware()
11439 tp->fw_needed = NULL; in tg3_request_firmware()
11445 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11449 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11453 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11464 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11465 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11466 if (!tp->rxq_cnt) in tg3_enable_msix()
11467 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11468 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11469 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11471 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11475 if (!tp->txq_req) in tg3_enable_msix()
11476 tp->txq_cnt = 1; in tg3_enable_msix()
11478 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11480 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11485 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11488 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11489 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11490 tp->irq_cnt, rc); in tg3_enable_msix()
11491 tp->irq_cnt = rc; in tg3_enable_msix()
11492 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11493 if (tp->txq_cnt) in tg3_enable_msix()
11494 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11497 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11498 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11500 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11501 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11505 if (tp->irq_cnt == 1) in tg3_enable_msix()
11510 if (tp->txq_cnt > 1) in tg3_enable_msix()
11513 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11525 netdev_warn(tp->dev, in tg3_ints_init()
11532 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11537 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11545 tp->irq_cnt = 1; in tg3_ints_init()
11546 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11549 if (tp->irq_cnt == 1) { in tg3_ints_init()
11550 tp->txq_cnt = 1; in tg3_ints_init()
11551 tp->rxq_cnt = 1; in tg3_ints_init()
11552 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11553 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11560 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11562 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11572 struct net_device *dev = tp->dev; in tg3_start()
11594 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11597 for (i--; i >= 0; i--) { in tg3_start()
11598 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11600 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11662 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11663 tg3_set_loopback(dev, dev->features); in tg3_start()
11668 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11669 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11670 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11707 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11708 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11709 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11724 if (tp->pcierr_recovery) { in tg3_open()
11727 return -EAGAIN; in tg3_open()
11730 if (tp->fw_needed) { in tg3_open()
11734 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11735 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11736 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11737 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11738 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11744 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11747 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11766 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11770 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11780 if (tp->pcierr_recovery) { in tg3_close()
11783 return -EAGAIN; in tg3_close()
11788 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11798 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11803 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11805 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11817 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11819 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11822 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11826 estats->member = old_estats->member + \
11827 get_stat64(&hw_stats->member)
11831 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11832 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11915 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11916 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11918 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
11919 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
11920 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
11921 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
11923 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
11924 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
11925 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
11926 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
11928 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
11929 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
11930 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
11931 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
11933 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
11934 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
11935 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
11936 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
11937 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
11938 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
11939 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11941 stats->multicast = old_stats->multicast + in tg3_get_nstats()
11942 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
11943 stats->collisions = old_stats->collisions + in tg3_get_nstats()
11944 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
11946 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
11947 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
11948 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
11950 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
11951 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
11952 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
11953 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11954 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
11955 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
11957 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
11960 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
11961 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
11963 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11964 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11977 regs->version = 0; in tg3_get_regs()
11981 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11995 return tp->nvram_size; in tg3_get_eeprom_len()
12007 return -EINVAL; in tg3_get_eeprom()
12009 offset = eeprom->offset; in tg3_get_eeprom()
12010 len = eeprom->len; in tg3_get_eeprom()
12011 eeprom->len = 0; in tg3_get_eeprom()
12013 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12031 b_count = 4 - b_offset; in tg3_get_eeprom()
12036 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12040 len -= b_count; in tg3_get_eeprom()
12042 eeprom->len += b_count; in tg3_get_eeprom()
12046 pd = &data[eeprom->len]; in tg3_get_eeprom()
12047 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12051 i -= 4; in tg3_get_eeprom()
12052 eeprom->len += i; in tg3_get_eeprom()
12058 eeprom->len += i; in tg3_get_eeprom()
12059 ret = -EINTR; in tg3_get_eeprom()
12065 eeprom->len += i; in tg3_get_eeprom()
12069 pd = &data[eeprom->len]; in tg3_get_eeprom()
12071 b_offset = offset + len - b_count; in tg3_get_eeprom()
12076 eeprom->len += b_count; in tg3_get_eeprom()
12098 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12099 return -EINVAL; in tg3_set_eeprom()
12101 offset = eeprom->offset; in tg3_set_eeprom()
12102 len = eeprom->len; in tg3_set_eeprom()
12106 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12120 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12129 return -ENOMEM; in tg3_set_eeprom()
12133 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12134 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12153 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12154 return -EAGAIN; in tg3_get_link_ksettings()
12155 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12163 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12167 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12173 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12176 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12178 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12181 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12183 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12184 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12190 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12194 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12197 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12198 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12199 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12201 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12202 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12204 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12205 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12206 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12208 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12211 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12212 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12213 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12215 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12216 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12224 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12229 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12230 return -EAGAIN; in tg3_set_link_ksettings()
12231 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12235 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12236 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12237 return -EINVAL; in tg3_set_link_ksettings()
12239 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12240 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12241 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12242 return -EINVAL; in tg3_set_link_ksettings()
12245 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12247 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12252 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12256 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12266 return -EINVAL; in tg3_set_link_ksettings()
12277 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12279 return -EINVAL; in tg3_set_link_ksettings()
12281 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12282 return -EINVAL; in tg3_set_link_ksettings()
12286 return -EINVAL; in tg3_set_link_ksettings()
12292 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12293 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12294 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12296 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12297 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12299 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12300 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12301 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12304 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12320 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12321 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12322 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12329 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12330 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12332 wol->supported = 0; in tg3_get_wol()
12333 wol->wolopts = 0; in tg3_get_wol()
12334 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12335 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12336 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12342 struct device *dp = &tp->pdev->dev; in tg3_set_wol() local
12344 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12345 return -EINVAL; in tg3_set_wol()
12346 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12347 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12348 return -EINVAL; in tg3_set_wol()
12350 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12352 if (device_may_wakeup(dp)) in tg3_set_wol()
12363 return tp->msg_enable; in tg3_get_msglevel()
12369 tp->msg_enable = value; in tg3_set_msglevel()
12378 return -EAGAIN; in tg3_nway_reset()
12380 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12381 return -EINVAL; in tg3_nway_reset()
12386 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12387 return -EAGAIN; in tg3_nway_reset()
12388 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12392 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12393 r = -EINVAL; in tg3_nway_reset()
12397 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12402 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12412 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12414 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12416 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12418 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12420 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12422 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12424 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12426 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12435 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12436 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12437 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12438 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12440 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12441 return -EINVAL; in tg3_set_ringparam()
12451 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12454 tp->rx_pending > 63) in tg3_set_ringparam()
12455 tp->rx_pending = 63; in tg3_set_ringparam()
12458 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12460 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12461 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12488 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12490 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12491 epause->rx_pause = 1; in tg3_get_pauseparam()
12493 epause->rx_pause = 0; in tg3_get_pauseparam()
12495 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12496 epause->tx_pause = 1; in tg3_get_pauseparam()
12498 epause->tx_pause = 0; in tg3_get_pauseparam()
12507 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12513 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12516 return -EINVAL; in tg3_set_pauseparam()
12518 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12519 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12520 if (epause->rx_pause) { in tg3_set_pauseparam()
12521 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12523 if (epause->tx_pause) { in tg3_set_pauseparam()
12524 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12526 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12527 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12530 if (epause->autoneg) in tg3_set_pauseparam()
12535 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12536 if (phydev->autoneg) { in tg3_set_pauseparam()
12547 if (!epause->autoneg) in tg3_set_pauseparam()
12560 if (epause->autoneg) in tg3_set_pauseparam()
12564 if (epause->rx_pause) in tg3_set_pauseparam()
12565 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12567 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12568 if (epause->tx_pause) in tg3_set_pauseparam()
12569 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12571 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12589 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12602 return -EOPNOTSUPP; in tg3_get_sset_count()
12612 return -EOPNOTSUPP; in tg3_get_rxnfc()
12614 switch (info->cmd) { in tg3_get_rxnfc()
12616 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12617 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12619 info->data = num_online_cpus(); in tg3_get_rxnfc()
12620 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12621 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12627 return -EOPNOTSUPP; in tg3_get_rxnfc()
12653 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12669 return -EOPNOTSUPP; in tg3_set_rxfh()
12675 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12696 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12697 channel->max_tx = tp->txq_max; in tg3_get_channels()
12700 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12701 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12703 if (tp->rxq_req) in tg3_get_channels()
12704 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12706 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12708 if (tp->txq_req) in tg3_get_channels()
12709 channel->tx_count = tp->txq_req; in tg3_get_channels()
12711 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12721 return -EOPNOTSUPP; in tg3_set_channels()
12723 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12724 channel->tx_count > tp->txq_max) in tg3_set_channels()
12725 return -EINVAL; in tg3_set_channels()
12727 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12728 tp->txq_req = channel->tx_count; in tg3_set_channels()
12782 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12794 if (tp->hw_stats) in tg3_get_ethtool_stats()
12842 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12843 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12856 cnt = pci_read_vpd(tp->pdev, pos, in tg3_vpd_readblock()
12857 len - pos, ptr); in tg3_vpd_readblock()
12858 if (cnt == -ETIMEDOUT || cnt == -EINTR) in tg3_vpd_readblock()
12896 return -EIO; in tg3_test_nvram()
12923 return -EIO; in tg3_test_nvram()
12930 return -EIO; in tg3_test_nvram()
12934 return -ENOMEM; in tg3_test_nvram()
12936 err = -EIO; in tg3_test_nvram()
12968 err = -EIO; in tg3_test_nvram()
13002 err = -EIO; in tg3_test_nvram()
13015 err = -EIO; in tg3_test_nvram()
13031 return -ENOMEM; in tg3_test_nvram()
13072 if (!netif_running(tp->dev)) in tg3_test_link()
13073 return -ENODEV; in tg3_test_link()
13075 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13081 if (tp->link_up) in tg3_test_link()
13088 return -EIO; in tg3_test_link()
13269 /* Determine the read-only value. */ in tg3_test_registers()
13272 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13279 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13284 * make sure the read-only bits are not changed and the in tg3_test_registers()
13291 /* Test the read-only bits. */ in tg3_test_registers()
13306 netdev_err(tp->dev, in tg3_test_registers()
13309 return -EIO; in tg3_test_registers()
13325 return -EIO; in tg3_do_mem_test()
13435 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13437 tnapi = &tp->napi[0]; in tg3_run_loopback()
13438 rnapi = &tp->napi[0]; in tg3_run_loopback()
13439 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13441 rnapi = &tp->napi[1]; in tg3_run_loopback()
13443 tnapi = &tp->napi[1]; in tg3_run_loopback()
13445 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13447 err = -EIO; in tg3_run_loopback()
13450 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13452 return -ENOMEM; in tg3_run_loopback()
13455 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13470 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13474 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13485 th->check = 0; in tg3_run_loopback()
13516 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); in tg3_run_loopback()
13517 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
13519 return -EIO; in tg3_run_loopback()
13522 val = tnapi->tx_prod; in tg3_run_loopback()
13523 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13524 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13526 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13527 rnapi->coal_now); in tg3_run_loopback()
13531 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13536 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13538 return -EIO; in tg3_run_loopback()
13541 tnapi->tx_prod++; in tg3_run_loopback()
13546 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13547 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13553 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13558 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13559 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13560 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13565 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13568 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13576 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13577 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13578 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13580 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13581 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13584 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13585 - ETH_FCS_LEN; in tg3_run_loopback()
13591 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13598 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13599 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13605 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13606 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13609 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13610 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13615 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, in tg3_run_loopback()
13642 int err = -EIO; in tg3_test_loopback()
13646 if (tp->dma_limit) in tg3_test_loopback()
13647 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13649 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13650 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13652 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13678 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13697 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13741 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13742 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13747 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13750 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13759 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13761 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13763 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13773 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13777 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13780 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13798 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13802 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13807 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13812 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13815 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13820 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13839 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13850 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13852 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13853 return -EFAULT; in tg3_hwtstamp_set()
13856 return -EINVAL; in tg3_hwtstamp_set()
13860 return -ERANGE; in tg3_hwtstamp_set()
13864 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13867 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13871 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13875 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13879 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13883 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13887 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13891 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13895 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13899 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13903 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13907 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13911 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13915 return -ERANGE; in tg3_hwtstamp_set()
13918 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13920 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13927 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13928 -EFAULT : 0; in tg3_hwtstamp_set()
13937 return -EOPNOTSUPP; in tg3_hwtstamp_get()
13943 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13985 return -ERANGE; in tg3_hwtstamp_get()
13988 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
13989 -EFAULT : 0; in tg3_hwtstamp_get()
14000 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14001 return -EAGAIN; in tg3_ioctl()
14002 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14008 data->phy_id = tp->phy_addr; in tg3_ioctl()
14014 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14018 return -EAGAIN; in tg3_ioctl()
14020 spin_lock_bh(&tp->lock); in tg3_ioctl()
14021 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14022 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14023 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14025 data->val_out = mii_regval; in tg3_ioctl()
14031 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14035 return -EAGAIN; in tg3_ioctl()
14037 spin_lock_bh(&tp->lock); in tg3_ioctl()
14038 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14039 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14040 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14054 return -EOPNOTSUPP; in tg3_ioctl()
14061 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14078 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14079 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14080 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14081 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14082 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14083 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14084 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14085 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14086 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14087 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14088 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14089 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14090 return -EINVAL; in tg3_set_coalesce()
14093 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14094 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14095 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14096 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14097 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14098 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14099 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14100 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14101 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14105 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14115 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14116 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14117 return -EOPNOTSUPP; in tg3_set_eee()
14120 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14121 netdev_warn(tp->dev, in tg3_set_eee()
14123 return -EINVAL; in tg3_set_eee()
14126 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14127 netdev_warn(tp->dev, in tg3_set_eee()
14130 return -EINVAL; in tg3_set_eee()
14133 tp->eee = *edata; in tg3_set_eee()
14135 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14138 if (netif_running(tp->dev)) { in tg3_set_eee()
14152 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14153 netdev_warn(tp->dev, in tg3_get_eee()
14155 return -EOPNOTSUPP; in tg3_get_eee()
14158 *edata = tp->eee; in tg3_get_eee()
14209 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14210 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14211 *stats = tp->net_stats_prev; in tg3_get_stats64()
14212 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14217 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14235 dev->mtu = new_mtu; in tg3_set_mtu()
14321 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14338 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14348 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14367 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14371 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14374 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14377 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14381 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14400 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14401 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14405 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14406 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14409 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14410 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14414 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14415 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14419 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14420 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14424 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14425 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14429 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14430 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14439 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14442 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14445 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14448 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14451 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14454 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14457 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14475 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14479 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14486 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14496 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14521 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14524 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14527 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14530 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14533 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14539 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14542 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14544 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14548 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14552 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14570 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14572 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14581 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14584 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14589 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14592 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14619 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14623 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14633 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14636 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14641 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14648 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14654 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14660 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14666 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14674 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14676 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14688 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14690 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14702 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14710 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14714 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14718 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14725 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14731 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14734 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14737 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14747 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14761 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14763 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14775 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14785 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14788 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14802 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14813 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14816 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14826 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14849 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14850 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14855 tp->nvram_size = in tg3_get_5720_nvram_info()
14879 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14885 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14887 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14901 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14909 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14914 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14918 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14922 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14944 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14953 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14959 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14965 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14969 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14979 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15022 netdev_warn(tp->dev, in tg3_nvram_init()
15029 tp->nvram_size = 0; in tg3_nvram_init()
15055 if (tp->nvram_size == 0) in tg3_nvram_init()
15144 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15146 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15156 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15157 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15174 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15187 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15220 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15223 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15225 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15237 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15241 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15245 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15252 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15257 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15260 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15265 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15271 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15275 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15277 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15285 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15286 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15289 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15293 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15295 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15296 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15313 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15320 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15324 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15326 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15329 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15335 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15346 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15348 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15359 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15363 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15366 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15399 return -EBUSY; in tg3_ape_otp_read()
15418 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15422 * configuration is a 32-bit value that straddles the alignment boundary.
15423 * We do two 32-bit reads and then shift and merge the results.
15455 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15456 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15461 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15470 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15471 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15472 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15473 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15474 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15475 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15477 tp->old_link = -1; in tg3_phy_init_link_config()
15488 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15491 switch (tp->pci_fn) { in tg3_phy_probe()
15493 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15496 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15499 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15502 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15508 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15509 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15510 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15525 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15539 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15541 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15543 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15545 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15557 tp->phy_id = p->phy_id; in tg3_phy_probe()
15566 return -ENODEV; in tg3_phy_probe()
15569 if (!tp->phy_id || in tg3_phy_probe()
15570 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15571 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15584 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15586 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15588 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15590 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15591 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15592 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15597 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15598 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15615 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15616 tp->link_config.flowctrl); in tg3_phy_probe()
15624 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15678 if (len >= sizeof(tp->fw_ver)) in tg3_read_vpd()
15679 len = sizeof(tp->fw_ver) - 1; in tg3_read_vpd()
15680 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15681 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, in tg3_read_vpd()
15698 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15702 if (tp->board_part_number[0]) in tg3_read_vpd()
15707 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15708 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15709 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15710 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15711 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15715 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15716 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15717 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15718 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15719 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15720 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15721 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15722 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15726 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15727 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15728 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15729 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15730 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15731 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15732 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15733 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15734 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15735 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15736 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15737 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15741 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15742 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15743 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15744 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15745 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15746 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15747 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15748 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15752 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15755 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15795 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15798 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15802 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15808 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15819 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15837 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15844 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15884 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15885 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15889 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15890 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15891 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15915 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15923 offset += val - start; in tg3_read_mgmtfw_ver()
15925 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15927 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15928 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15937 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15938 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15942 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15973 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15978 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15980 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16008 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16009 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16018 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16022 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16047 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16070 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16073 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16074 if (peer && peer != tp->pdev) in tg3_find_peer()
16078 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16079 * tp->pdev in that case. in tg3_find_peer()
16082 peer = tp->pdev; in tg3_find_peer()
16097 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16106 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16107 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16108 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16109 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16110 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16111 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16112 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16113 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16114 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16115 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16116 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16118 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16119 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16120 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16122 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16123 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16125 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16126 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16132 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16139 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16142 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16190 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16193 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16195 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16220 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16222 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16224 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16229 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16231 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16233 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16234 tp->misc_host_ctrl); in tg3_get_invariants()
16244 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16247 * non-zero address during special cycles. However, only in tg3_get_invariants()
16248 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16275 while (pci_id->vendor != 0) { in tg3_get_invariants()
16276 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16282 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16283 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16286 if (bridge->subordinate && in tg3_get_invariants()
16287 (bridge->subordinate->number == in tg3_get_invariants()
16288 tp->pdev->bus->number)) { in tg3_get_invariants()
16308 while (pci_id->vendor != 0) { in tg3_get_invariants()
16309 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16310 pci_id->device, in tg3_get_invariants()
16316 if (bridge->subordinate && in tg3_get_invariants()
16317 (bridge->subordinate->number <= in tg3_get_invariants()
16318 tp->pdev->bus->number) && in tg3_get_invariants()
16319 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16320 tp->pdev->bus->number)) { in tg3_get_invariants()
16329 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16330 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16331 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16336 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16344 if (bridge && bridge->subordinate && in tg3_get_invariants()
16345 (bridge->subordinate->number <= in tg3_get_invariants()
16346 tp->pdev->bus->number) && in tg3_get_invariants()
16347 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16348 tp->pdev->bus->number)) { in tg3_get_invariants()
16358 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16380 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16382 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16398 tp->fw_needed = NULL; in tg3_get_invariants()
16402 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16405 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16407 tp->irq_max = 1; in tg3_get_invariants()
16415 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16425 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16429 tp->txq_max = 1; in tg3_get_invariants()
16430 tp->rxq_max = 1; in tg3_get_invariants()
16431 if (tp->irq_max > 1) { in tg3_get_invariants()
16432 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16437 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16445 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16462 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16465 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16470 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16492 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16493 if (!tp->pcix_cap) { in tg3_get_invariants()
16494 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16495 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16496 return -EIO; in tg3_get_invariants()
16513 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16514 &tp->pci_cacheline_sz); in tg3_get_invariants()
16515 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16516 &tp->pci_lat_timer); in tg3_get_invariants()
16518 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16519 tp->pci_lat_timer = 64; in tg3_get_invariants()
16520 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16521 tp->pci_lat_timer); in tg3_get_invariants()
16524 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16533 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16547 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16548 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16552 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16553 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16557 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16559 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16568 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16572 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16576 tp->read32 = tg3_read32; in tg3_get_invariants()
16577 tp->write32 = tg3_write32; in tg3_get_invariants()
16578 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16579 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16580 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16581 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16585 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16596 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16600 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16602 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16606 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16607 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16608 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16609 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16610 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16611 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16613 iounmap(tp->regs); in tg3_get_invariants()
16614 tp->regs = NULL; in tg3_get_invariants()
16616 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16618 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16621 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16622 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16623 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16624 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16627 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16641 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16645 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16646 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16648 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16658 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16660 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16665 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16666 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16682 tp->fw_needed = NULL; in tg3_get_invariants()
16692 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16696 tp->ape_hb_interval = in tg3_get_invariants()
16700 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16705 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16708 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16711 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16714 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16719 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16721 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16724 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16727 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16732 tp->grc_local_ctrl |= in tg3_get_invariants()
16741 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16755 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16762 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16763 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16764 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16768 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16770 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16773 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16781 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16782 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16783 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16784 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16785 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16787 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16792 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16793 if (tp->phy_otp == 0) in tg3_get_invariants()
16794 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16798 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16800 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16802 tp->coalesce_mode = 0; in tg3_get_invariants()
16805 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16812 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16813 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16836 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16846 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16860 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16876 tp->fw_needed = NULL; in tg3_get_invariants()
16890 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16893 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16894 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16895 tp->misc_host_ctrl); in tg3_get_invariants()
16900 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16902 tp->mac_mode = 0; in tg3_get_invariants()
16905 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16909 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16917 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16918 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16921 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16923 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16939 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16941 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16942 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16947 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16955 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16956 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16959 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16961 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16965 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16966 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16967 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16969 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16977 tp->rx_std_max_post = 8; in tg3_get_invariants()
16980 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16988 struct net_device *dev = tp->dev; in tg3_get_device_address()
16993 if (!eth_platform_get_mac_address(&tp->pdev->dev, dev->dev_addr)) in tg3_get_device_address()
16997 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); in tg3_get_device_address()
16998 if (!err && is_valid_ether_addr(&dev->dev_addr[0])) in tg3_get_device_address()
17012 if (tp->pci_fn & 1) in tg3_get_device_address()
17014 if (tp->pci_fn > 1) in tg3_get_device_address()
17022 dev->dev_addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17023 dev->dev_addr[1] = (hi >> 0) & 0xff; in tg3_get_device_address()
17026 dev->dev_addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17027 dev->dev_addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17028 dev->dev_addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17029 dev->dev_addr[5] = (lo >> 0) & 0xff; in tg3_get_device_address()
17032 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); in tg3_get_device_address()
17039 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); in tg3_get_device_address()
17040 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); in tg3_get_device_address()
17047 dev->dev_addr[5] = lo & 0xff; in tg3_get_device_address()
17048 dev->dev_addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17049 dev->dev_addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17050 dev->dev_addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17051 dev->dev_addr[1] = hi & 0xff; in tg3_get_device_address()
17052 dev->dev_addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17056 if (!is_valid_ether_addr(&dev->dev_addr[0])) in tg3_get_device_address()
17057 return -EINVAL; in tg3_get_device_address()
17070 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17103 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17106 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17107 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17237 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17256 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17258 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17260 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17267 ret = -ENODEV; in tg3_do_test_dma()
17299 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17302 ret = -ENOMEM; in tg3_test_dma()
17306 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17309 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17316 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17320 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17322 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17335 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17337 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17342 tp->dma_rwctrl |= in tg3_test_dma()
17348 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17351 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17353 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17357 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17361 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17366 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17376 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17378 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17381 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17391 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17392 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17393 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17404 dev_err(&tp->pdev->dev, in tg3_test_dma()
17413 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17423 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17425 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17426 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17427 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17430 dev_err(&tp->pdev->dev, in tg3_test_dma()
17433 ret = -ENODEV; in tg3_test_dma()
17444 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17451 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17452 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17455 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17458 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17462 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17470 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17472 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17477 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17479 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17481 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17484 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17486 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17488 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17491 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17493 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17497 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17499 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17501 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17504 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17506 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17508 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17511 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17513 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17515 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17519 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17520 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17525 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17585 strcat(str, ":32-bit"); in tg3_bus_string()
17587 strcat(str, ":64-bit"); in tg3_bus_string()
17593 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17596 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17597 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17598 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17599 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17600 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17601 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17602 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17603 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17604 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17605 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17607 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17609 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17610 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17611 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17612 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17616 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17617 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17618 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17635 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17641 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17649 err = -ENOMEM; in tg3_init_one()
17653 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17656 tp->pdev = pdev; in tg3_init_one()
17657 tp->dev = dev; in tg3_init_one()
17658 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17659 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17660 tp->irq_sync = 1; in tg3_init_one()
17661 tp->pcierr_recovery = false; in tg3_init_one()
17664 tp->msg_enable = tg3_debug; in tg3_init_one()
17666 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17686 tp->misc_host_ctrl = in tg3_init_one()
17692 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17696 * are running in big-endian mode. in tg3_init_one()
17698 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17701 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17703 spin_lock_init(&tp->lock); in tg3_init_one()
17704 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17705 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17707 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17708 if (!tp->regs) { in tg3_init_one()
17709 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17710 err = -ENOMEM; in tg3_init_one()
17714 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17715 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17716 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17717 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17718 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17719 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17720 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17721 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17723 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17724 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17725 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17726 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17727 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17728 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17730 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17731 if (!tp->aperegs) { in tg3_init_one()
17732 dev_err(&pdev->dev, in tg3_init_one()
17734 err = -ENOMEM; in tg3_init_one()
17739 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17740 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17742 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17743 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17744 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17745 dev->irq = pdev->irq; in tg3_init_one()
17749 dev_err(&pdev->dev, in tg3_init_one()
17755 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17756 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17757 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17778 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17787 dev_err(&pdev->dev, in tg3_init_one()
17826 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17828 dev->vlan_features |= features; in tg3_init_one()
17832 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17840 dev->hw_features |= features; in tg3_init_one()
17841 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17843 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17844 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17845 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17851 tp->rx_pending = 63; in tg3_init_one()
17856 dev_err(&pdev->dev, in tg3_init_one()
17864 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17865 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17867 tnapi->tp = tp; in tg3_init_one()
17868 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17870 tnapi->int_mbox = intmbx; in tg3_init_one()
17876 tnapi->consmbox = rcvmbx; in tg3_init_one()
17877 tnapi->prodmbox = sndmbx; in tg3_init_one()
17880 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17882 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17900 sndmbx -= 0x4; in tg3_init_one()
17920 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17939 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
17945 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17946 &tp->pdev->dev); in tg3_init_one()
17947 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17948 tp->ptp_clock = NULL; in tg3_init_one()
17952 tp->board_part_number, in tg3_init_one()
17955 dev->dev_addr); in tg3_init_one()
17957 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17960 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17961 ethtype = "10/100Base-TX"; in tg3_init_one()
17962 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17963 ethtype = "1000Base-SX"; in tg3_init_one()
17965 ethtype = "10/100/1000Base-T"; in tg3_init_one()
17970 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17971 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17975 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
17977 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17980 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
17981 tp->dma_rwctrl, in tg3_init_one()
17982 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
17983 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
17990 if (tp->aperegs) { in tg3_init_one()
17991 iounmap(tp->aperegs); in tg3_init_one()
17992 tp->aperegs = NULL; in tg3_init_one()
17996 if (tp->regs) { in tg3_init_one()
17997 iounmap(tp->regs); in tg3_init_one()
17998 tp->regs = NULL; in tg3_init_one()
18022 release_firmware(tp->fw); in tg3_remove_one()
18032 if (tp->aperegs) { in tg3_remove_one()
18033 iounmap(tp->aperegs); in tg3_remove_one()
18034 tp->aperegs = NULL; in tg3_remove_one()
18036 if (tp->regs) { in tg3_remove_one()
18037 iounmap(tp->regs); in tg3_remove_one()
18038 tp->regs = NULL; in tg3_remove_one()
18122 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18162 * tg3_io_error_detected - called when PCI error is detected
18181 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18186 tp->pcierr_recovery = true; in tg3_io_error_detected()
18221 * tg3_io_slot_reset - called after the pci bus has been reset.
18224 * Restart the card from scratch, as if from a cold-boot.
18239 dev_err(&pdev->dev, in tg3_io_slot_reset()
18240 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18270 * tg3_io_resume - called when traffic can start flowing again.
18308 tp->pcierr_recovery = false; in tg3_io_resume()