789 		trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);  in bnx2x_fw_dump_lvl()
2808 		vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);  in bnx2x_handle_afex_cmd()
2815 		vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);  in bnx2x_handle_afex_cmd()
2816 		addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);  in bnx2x_handle_afex_cmd()
2825 		addr_to_write = SHMEM2_RD(bp,  in bnx2x_handle_afex_cmd()
2827 		stats_type = SHMEM2_RD(bp,  in bnx2x_handle_afex_cmd()
3576 	u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);  in bnx2x_handle_drv_info_req()
3631 			u32 indication = SHMEM2_RD(bp, mfw_drv_indication);  in bnx2x_handle_drv_info_req()
3739 	valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);  in bnx2x_update_mfw_dump()
6990 	if (SHMEM2_RD(bp, size) >  in bnx2x__common_init_phy()
6997 			SHMEM2_RD(bp, other_shmem_base_addr);  in bnx2x__common_init_phy()
6999 			SHMEM2_RD(bp, other_shmem2_base_addr);  in bnx2x__common_init_phy()
11006 	if (SHMEM2_RD(bp, size) >  in bnx2x_get_common_hwinfo()
12004 			       bp->common.shmem2_base, SHMEM2_RD(bp, size),  in bnx2x_get_hwinfo()
12008 			bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);  in bnx2x_get_hwinfo()
12069 					mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);  in bnx2x_get_hwinfo()
12415 	    SHMEM2_RD(bp, dcbx_lldp_params_offset) &&  in bnx2x_init_bp()
12416 	    SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&  in bnx2x_init_bp()
12417 	    SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {  in bnx2x_init_bp()
14293 			v = SHMEM2_RD(bp,  in bnx2x_io_slot_reset()
14791 			u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);  in bnx2x_drv_ctl()
14811 			scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);  in bnx2x_drv_ctl()
14834 			cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);  in bnx2x_drv_ctl()
14895 	offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);  in bnx2x_get_fc_npiv()