12 bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw)  in aq_mdio_busy_wait()  argument
17 	err = readx_poll_timeout_atomic(hw_atl_mdio_busy_get, aq_hw,  in aq_mdio_busy_wait()
26 u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr)  in aq_mdio_read_word()  argument
28 	u16 phy_addr = aq_hw->phy_id << 5 | mmd;  in aq_mdio_read_word()
31 	hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<  in aq_mdio_read_word()
34 	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |  in aq_mdio_read_word()
39 	aq_mdio_busy_wait(aq_hw);  in aq_mdio_read_word()
42 	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |  in aq_mdio_read_word()
47 	aq_mdio_busy_wait(aq_hw);  in aq_mdio_read_word()
49 	return (u16)hw_atl_glb_mdio_iface5_get(aq_hw);  in aq_mdio_read_word()
52 void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data)  in aq_mdio_write_word()  argument
54 	u16 phy_addr = aq_hw->phy_id << 5 | mmd;  in aq_mdio_write_word()
57 	hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<  in aq_mdio_write_word()
60 	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |  in aq_mdio_write_word()
65 	aq_mdio_busy_wait(aq_hw);  in aq_mdio_write_word()
67 	hw_atl_glb_mdio_iface3_set(aq_hw, (data & HW_ATL_MDIO_WRITE_DATA_MSK) <<  in aq_mdio_write_word()
70 	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |  in aq_mdio_write_word()
75 	aq_mdio_busy_wait(aq_hw);  in aq_mdio_write_word()
78 u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address)  in aq_phy_read_reg()  argument
83 	err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,  in aq_phy_read_reg()
91 	err = aq_mdio_read_word(aq_hw, mmd, address);  in aq_phy_read_reg()
93 	hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);  in aq_phy_read_reg()
99 void aq_phy_write_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address, u16 data)  in aq_phy_write_reg()  argument
104 	err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,  in aq_phy_write_reg()
109 	aq_mdio_write_word(aq_hw, mmd, address, data);  in aq_phy_write_reg()
110 	hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);  in aq_phy_write_reg()
113 bool aq_phy_init_phy_id(struct aq_hw_s *aq_hw)  in aq_phy_init_phy_id()  argument
117 	for (aq_hw->phy_id = 0; aq_hw->phy_id < HW_ATL_PHY_ID_MAX;  in aq_phy_init_phy_id()
118 	     ++aq_hw->phy_id) {  in aq_phy_init_phy_id()
120 		val = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);  in aq_phy_init_phy_id()
129 bool aq_phy_init(struct aq_hw_s *aq_hw)  in aq_phy_init()  argument
133 	if (aq_hw->phy_id == HW_ATL_PHY_ID_MAX)  in aq_phy_init()
134 		if (!aq_phy_init_phy_id(aq_hw))  in aq_phy_init()
141 	dev_id = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 2);  in aq_phy_init()
143 	dev_id |= aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);  in aq_phy_init()
146 		aq_hw->phy_id = HW_ATL_PHY_ID_MAX;  in aq_phy_init()
153 void aq_phy_disable_ptp(struct aq_hw_s *aq_hw)  in aq_phy_disable_ptp()  argument
165 		val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1,  in aq_phy_disable_ptp()
168 		aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1,  in aq_phy_disable_ptp()