Lines Matching +full:apb3 +full:- +full:bus
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
125 #include "xgbe-common.h"
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
138 DBGPR("-->xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
150 DBGPR("<--xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
161 DBGPR("-->xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
173 DBGPR("<--xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
184 pbl = pdata->pbl; in xgbe_config_pbl_val()
186 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
191 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
195 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
199 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
211 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
212 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
216 pdata->tx_osp_mode); in xgbe_config_osp_mode()
226 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
236 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
247 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
258 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
268 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
269 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
273 pdata->rx_riwt); in xgbe_config_rx_coalesce()
288 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
289 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
293 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
301 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
302 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); in xgbe_config_tso_mode()
313 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
314 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
329 mutex_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
332 ret = -EBUSY; in xgbe_write_rss_reg()
344 while (wait--) { in xgbe_write_rss_reg()
351 ret = -EBUSY; in xgbe_write_rss_reg()
354 mutex_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in xgbe_write_rss_hash_key()
362 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
365 while (key_regs--) { in xgbe_write_rss_hash_key()
380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
383 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
413 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
414 return -EOPNOTSUPP; in xgbe_enable_rss()
427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
437 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
438 return -EOPNOTSUPP; in xgbe_disable_rss()
449 if (!pdata->hw_feat.rss) in xgbe_config_rss()
452 if (pdata->netdev->features & NETIF_F_RXHASH) in xgbe_config_rss()
458 netdev_err(pdata->netdev, in xgbe_config_rss()
469 if (pdata->prio2q_map[prio] != queue) in xgbe_is_pfc_queue()
473 tc = pdata->ets->prio_tc[prio]; in xgbe_is_pfc_queue()
476 if (pdata->pfc->pfc_en & (1 << tc)) in xgbe_is_pfc_queue()
486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); in xgbe_set_vxlan_id()
488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", in xgbe_set_vxlan_id()
489 pdata->vxlan_port); in xgbe_set_vxlan_id()
494 if (!pdata->hw_feat.vxn) in xgbe_enable_vxlan()
500 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ in xgbe_enable_vxlan()
507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); in xgbe_enable_vxlan()
512 if (!pdata->hw_feat.vxn) in xgbe_disable_vxlan()
518 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ in xgbe_disable_vxlan()
524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); in xgbe_disable_vxlan()
534 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
539 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_disable_tx_flow_control()
554 struct ieee_pfc *pfc = pdata->pfc; in xgbe_enable_tx_flow_control()
555 struct ieee_ets *ets = pdata->ets; in xgbe_enable_tx_flow_control()
561 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
564 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
576 netif_dbg(pdata, drv, pdata->netdev, in xgbe_enable_tx_flow_control()
583 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_enable_tx_flow_control()
617 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_tx_flow_control()
619 if (pdata->tx_pause || (pfc && pfc->pfc_en)) in xgbe_config_tx_flow_control()
629 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_rx_flow_control()
631 if (pdata->rx_pause || (pfc && pfc->pfc_en)) in xgbe_config_rx_flow_control()
641 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_flow_control()
647 (pfc && pfc->pfc_en) ? 1 : 0); in xgbe_config_flow_control()
656 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
658 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
660 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
662 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
663 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
670 channel->curr_ier = 0; in xgbe_enable_dma_interrupts()
673 * NIE - Normal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
674 * AIE - Abnormal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
675 * FBEE - Fatal Bus Error Enable in xgbe_enable_dma_interrupts()
678 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); in xgbe_enable_dma_interrupts()
679 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); in xgbe_enable_dma_interrupts()
681 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); in xgbe_enable_dma_interrupts()
682 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); in xgbe_enable_dma_interrupts()
684 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_dma_interrupts()
686 if (channel->tx_ring) { in xgbe_enable_dma_interrupts()
688 * TIE - Transmit Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
692 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
693 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
696 if (channel->rx_ring) { in xgbe_enable_dma_interrupts()
698 * RBUE - Receive Buffer Unavailable Enable in xgbe_enable_dma_interrupts()
699 * RIE - Receive Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
703 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_dma_interrupts()
704 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
705 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
709 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_dma_interrupts()
718 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
750 if (!pdata->vdata->ecc_support) in xgbe_enable_ecc_interrupts()
820 return -EINVAL; in xgbe_set_speed()
837 /* Check only C-TAG (0x8100) packets */ in xgbe_enable_rx_vlan_stripping()
840 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ in xgbe_enable_rx_vlan_stripping()
867 /* Only filter on the lower 12-bits of the VLAN tag */ in xgbe_enable_rx_vlan_filtering()
921 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { in xgbe_update_vlan_hash_table()
943 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", in xgbe_set_promiscuous_mode()
951 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_set_promiscuous_mode()
966 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", in xgbe_set_all_multicast_mode()
984 mac_addr[0] = ha->addr[0]; in xgbe_set_mac_reg()
985 mac_addr[1] = ha->addr[1]; in xgbe_set_mac_reg()
986 mac_addr[2] = ha->addr[2]; in xgbe_set_mac_reg()
987 mac_addr[3] = ha->addr[3]; in xgbe_set_mac_reg()
989 mac_addr[0] = ha->addr[4]; in xgbe_set_mac_reg()
990 mac_addr[1] = ha->addr[5]; in xgbe_set_mac_reg()
992 netif_dbg(pdata, drv, pdata->netdev, in xgbe_set_mac_reg()
994 ha->addr, *mac_reg); in xgbe_set_mac_reg()
1007 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_addn_addrs()
1013 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
1020 addn_macs--; in xgbe_set_mac_addn_addrs()
1028 addn_macs--; in xgbe_set_mac_addn_addrs()
1034 while (addn_macs--) in xgbe_set_mac_addn_addrs()
1040 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_hash_table()
1048 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); in xgbe_set_mac_hash_table()
1049 hash_table_count = pdata->hw_feat.hash_table_size / 32; in xgbe_set_mac_hash_table()
1054 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); in xgbe_set_mac_hash_table()
1060 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); in xgbe_set_mac_hash_table()
1075 if (pdata->hw_feat.hash_table_size) in xgbe_add_mac_addresses()
1099 struct net_device *netdev = pdata->netdev; in xgbe_config_rx_mode()
1102 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); in xgbe_config_rx_mode()
1103 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); in xgbe_config_rx_mode()
1118 return -EINVAL; in xgbe_clr_gpio()
1133 return -EINVAL; in xgbe_set_gpio()
1153 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1160 * The mmio interface is based on 16-bit offsets and values. All in xgbe_read_mmd_regs_v2()
1165 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1166 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1168 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1169 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1171 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1185 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1192 * The mmio interface is based on 16-bit offsets and values. All in xgbe_write_mmd_regs_v2()
1197 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1198 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1200 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1201 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1203 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1216 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1218 /* The PCS registers are accessed using mmio. The underlying APB3 in xgbe_read_mmd_regs_v1()
1223 * The mmio interface is based on 32-bit offsets and values. All in xgbe_read_mmd_regs_v1()
1227 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1230 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1244 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1246 /* The PCS registers are accessed using mmio. The underlying APB3 in xgbe_write_mmd_regs_v1()
1251 * The mmio interface is based on 32-bit offsets and values. All in xgbe_write_mmd_regs_v1()
1255 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1258 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1264 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1277 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1306 reinit_completion(&pdata->mdio_complete); in xgbe_write_ext_mii_regs()
1317 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_write_ext_mii_regs()
1318 netdev_err(pdata->netdev, "mdio write operation timed out\n"); in xgbe_write_ext_mii_regs()
1319 return -ETIMEDOUT; in xgbe_write_ext_mii_regs()
1330 reinit_completion(&pdata->mdio_complete); in xgbe_read_ext_mii_regs()
1340 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_read_ext_mii_regs()
1341 netdev_err(pdata->netdev, "mdio read operation timed out\n"); in xgbe_read_ext_mii_regs()
1342 return -ETIMEDOUT; in xgbe_read_ext_mii_regs()
1356 return -EINVAL; in xgbe_set_ext_mii_mode()
1362 return -EINVAL; in xgbe_set_ext_mii_mode()
1372 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); in xgbe_tx_complete()
1391 struct xgbe_ring_desc *rdesc = rdata->rdesc; in xgbe_tx_desc_reset()
1399 rdesc->desc0 = 0; in xgbe_tx_desc_reset()
1400 rdesc->desc1 = 0; in xgbe_tx_desc_reset()
1401 rdesc->desc2 = 0; in xgbe_tx_desc_reset()
1402 rdesc->desc3 = 0; in xgbe_tx_desc_reset()
1410 struct xgbe_ring *ring = channel->tx_ring; in xgbe_tx_desc_init()
1413 int start_index = ring->cur; in xgbe_tx_desc_init()
1415 DBGPR("-->tx_desc_init\n"); in xgbe_tx_desc_init()
1418 for (i = 0; i < ring->rdesc_count; i++) { in xgbe_tx_desc_init()
1426 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); in xgbe_tx_desc_init()
1431 upper_32_bits(rdata->rdesc_dma)); in xgbe_tx_desc_init()
1433 lower_32_bits(rdata->rdesc_dma)); in xgbe_tx_desc_init()
1435 DBGPR("<--tx_desc_init\n"); in xgbe_tx_desc_init()
1441 struct xgbe_ring_desc *rdesc = rdata->rdesc; in xgbe_rx_desc_reset()
1442 unsigned int rx_usecs = pdata->rx_usecs; in xgbe_rx_desc_reset()
1443 unsigned int rx_frames = pdata->rx_frames; in xgbe_rx_desc_reset()
1465 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; in xgbe_rx_desc_reset()
1466 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; in xgbe_rx_desc_reset()
1467 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); in xgbe_rx_desc_reset()
1468 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); in xgbe_rx_desc_reset()
1469 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); in xgbe_rx_desc_reset()
1470 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); in xgbe_rx_desc_reset()
1472 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); in xgbe_rx_desc_reset()
1480 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); in xgbe_rx_desc_reset()
1488 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_rx_desc_init()
1489 struct xgbe_ring *ring = channel->rx_ring; in xgbe_rx_desc_init()
1491 unsigned int start_index = ring->cur; in xgbe_rx_desc_init()
1494 DBGPR("-->rx_desc_init\n"); in xgbe_rx_desc_init()
1497 for (i = 0; i < ring->rdesc_count; i++) { in xgbe_rx_desc_init()
1505 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); in xgbe_rx_desc_init()
1510 upper_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1512 lower_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1515 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); in xgbe_rx_desc_init()
1517 lower_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1519 DBGPR("<--rx_desc_init\n"); in xgbe_rx_desc_init()
1532 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) in xgbe_update_tstamp_addend()
1536 netdev_err(pdata->netdev, in xgbe_update_tstamp_addend()
1551 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) in xgbe_set_tstamp_time()
1555 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); in xgbe_set_tstamp_time()
1574 if (pdata->vdata->tx_tstamp_workaround) { in xgbe_get_tx_tstamp()
1597 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && in xgbe_get_rx_tstamp()
1598 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { in xgbe_get_rx_tstamp()
1599 nsec = le32_to_cpu(rdesc->desc1); in xgbe_get_rx_tstamp()
1601 nsec |= le32_to_cpu(rdesc->desc0); in xgbe_get_rx_tstamp()
1603 packet->rx_tstamp = nsec; in xgbe_get_rx_tstamp()
1604 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_get_rx_tstamp()
1613 /* Set one nano-second accuracy */ in xgbe_config_tstamp()
1631 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); in xgbe_config_tstamp()
1635 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, in xgbe_config_tstamp()
1644 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_tx_start_xmit()
1652 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); in xgbe_tx_start_xmit()
1654 lower_32_bits(rdata->rdesc_dma)); in xgbe_tx_start_xmit()
1657 if (pdata->tx_usecs && !channel->tx_timer_active) { in xgbe_tx_start_xmit()
1658 channel->tx_timer_active = 1; in xgbe_tx_start_xmit()
1659 mod_timer(&channel->tx_timer, in xgbe_tx_start_xmit()
1660 jiffies + usecs_to_jiffies(pdata->tx_usecs)); in xgbe_tx_start_xmit()
1663 ring->tx.xmit_more = 0; in xgbe_tx_start_xmit()
1668 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_xmit()
1669 struct xgbe_ring *ring = channel->tx_ring; in xgbe_dev_xmit()
1672 struct xgbe_packet_data *packet = &ring->packet_data; in xgbe_dev_xmit()
1677 int start_index = ring->cur; in xgbe_dev_xmit()
1678 int cur_index = ring->cur; in xgbe_dev_xmit()
1681 DBGPR("-->xgbe_dev_xmit\n"); in xgbe_dev_xmit()
1683 tx_packets = packet->tx_packets; in xgbe_dev_xmit()
1684 tx_bytes = packet->tx_bytes; in xgbe_dev_xmit()
1686 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1688 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1690 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1692 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1695 if (tso && (packet->mss != ring->tx.cur_mss)) in xgbe_dev_xmit()
1700 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) in xgbe_dev_xmit()
1707 * - Tx frame count exceeds the frame count setting in xgbe_dev_xmit()
1708 * - Addition of Tx frame count to the frame count since the in xgbe_dev_xmit()
1711 * - No frame count setting specified (ethtool -C ethX tx-frames 0) in xgbe_dev_xmit()
1712 * - Addition of Tx frame count to the frame count since the in xgbe_dev_xmit()
1715 ring->coalesce_count += tx_packets; in xgbe_dev_xmit()
1716 if (!pdata->tx_frames) in xgbe_dev_xmit()
1718 else if (tx_packets > pdata->tx_frames) in xgbe_dev_xmit()
1720 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) in xgbe_dev_xmit()
1726 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1731 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1733 packet->mss); in xgbe_dev_xmit()
1736 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, in xgbe_dev_xmit()
1737 MSS, packet->mss); in xgbe_dev_xmit()
1740 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1744 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1747 ring->tx.cur_mss = packet->mss; in xgbe_dev_xmit()
1751 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1753 packet->vlan_ctag); in xgbe_dev_xmit()
1756 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1760 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1761 VT, packet->vlan_ctag); in xgbe_dev_xmit()
1764 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1767 ring->tx.cur_vlan_ctag = packet->vlan_ctag; in xgbe_dev_xmit()
1772 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1776 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1777 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1780 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, in xgbe_dev_xmit()
1781 rdata->skb_dma_len); in xgbe_dev_xmit()
1785 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, in xgbe_dev_xmit()
1789 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) in xgbe_dev_xmit()
1790 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); in xgbe_dev_xmit()
1793 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); in xgbe_dev_xmit()
1796 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); in xgbe_dev_xmit()
1800 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1804 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); in xgbe_dev_xmit()
1805 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, in xgbe_dev_xmit()
1806 packet->tcp_payload_len); in xgbe_dev_xmit()
1807 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, in xgbe_dev_xmit()
1808 packet->tcp_header_len / 4); in xgbe_dev_xmit()
1810 pdata->ext_stats.tx_tso_packets += tx_packets; in xgbe_dev_xmit()
1813 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); in xgbe_dev_xmit()
1817 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, in xgbe_dev_xmit()
1821 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, in xgbe_dev_xmit()
1822 packet->length); in xgbe_dev_xmit()
1826 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, in xgbe_dev_xmit()
1829 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; in xgbe_dev_xmit()
1832 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { in xgbe_dev_xmit()
1835 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1838 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1839 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1842 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, in xgbe_dev_xmit()
1843 rdata->skb_dma_len); in xgbe_dev_xmit()
1846 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1849 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); in xgbe_dev_xmit()
1853 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, in xgbe_dev_xmit()
1858 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); in xgbe_dev_xmit()
1862 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); in xgbe_dev_xmit()
1865 rdata->tx.packets = tx_packets; in xgbe_dev_xmit()
1866 rdata->tx.bytes = tx_bytes; in xgbe_dev_xmit()
1868 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; in xgbe_dev_xmit()
1869 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; in xgbe_dev_xmit()
1879 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1880 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1884 packet->rdesc_count, 1); in xgbe_dev_xmit()
1889 ring->cur = cur_index + 1; in xgbe_dev_xmit()
1891 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, in xgbe_dev_xmit()
1892 channel->queue_index))) in xgbe_dev_xmit()
1895 ring->tx.xmit_more = 1; in xgbe_dev_xmit()
1898 channel->name, start_index & (ring->rdesc_count - 1), in xgbe_dev_xmit()
1899 (ring->cur - 1) & (ring->rdesc_count - 1)); in xgbe_dev_xmit()
1901 DBGPR("<--xgbe_dev_xmit\n"); in xgbe_dev_xmit()
1906 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read()
1907 struct xgbe_ring *ring = channel->rx_ring; in xgbe_dev_read()
1910 struct xgbe_packet_data *packet = &ring->packet_data; in xgbe_dev_read()
1911 struct net_device *netdev = pdata->netdev; in xgbe_dev_read()
1914 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); in xgbe_dev_read()
1916 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); in xgbe_dev_read()
1917 rdesc = rdata->rdesc; in xgbe_dev_read()
1920 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) in xgbe_dev_read()
1927 xgbe_dump_rx_desc(pdata, ring, ring->cur); in xgbe_dev_read()
1929 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { in xgbe_dev_read()
1933 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1935 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1941 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); in xgbe_dev_read()
1944 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) in xgbe_dev_read()
1945 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1949 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { in xgbe_dev_read()
1950 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1952 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, in xgbe_dev_read()
1954 if (rdata->rx.hdr_len) in xgbe_dev_read()
1955 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1957 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1962 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { in xgbe_dev_read()
1963 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1966 packet->rss_hash = le32_to_cpu(rdesc->desc1); in xgbe_dev_read()
1968 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); in xgbe_dev_read()
1974 packet->rss_hash_type = PKT_HASH_TYPE_L4; in xgbe_dev_read()
1977 packet->rss_hash_type = PKT_HASH_TYPE_L3; in xgbe_dev_read()
1982 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) in xgbe_dev_read()
1986 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1990 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); in xgbe_dev_read()
1993 if (netdev->features & NETIF_F_RXCSUM) { in xgbe_dev_read()
1994 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1996 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2001 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { in xgbe_dev_read()
2002 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2004 pdata->ext_stats.rx_vxlan_packets++; in xgbe_dev_read()
2006 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); in xgbe_dev_read()
2010 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2017 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); in xgbe_dev_read()
2018 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); in xgbe_dev_read()
2024 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { in xgbe_dev_read()
2025 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2027 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, in xgbe_dev_read()
2030 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", in xgbe_dev_read()
2031 packet->vlan_ctag); in xgbe_dev_read()
2034 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, in xgbe_dev_read()
2038 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2040 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2042 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
2044 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2046 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
2048 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
2050 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, in xgbe_dev_read()
2055 pdata->ext_stats.rxq_packets[channel->queue_index]++; in xgbe_dev_read()
2056 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; in xgbe_dev_read()
2058 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, in xgbe_dev_read()
2059 ring->cur & (ring->rdesc_count - 1), ring->cur); in xgbe_dev_read()
2067 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); in xgbe_is_context_desc()
2073 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); in xgbe_is_last_desc()
2081 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
2084 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); in xgbe_enable_int()
2087 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); in xgbe_enable_int()
2090 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
2093 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_int()
2096 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); in xgbe_enable_int()
2099 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
2100 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
2103 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_int()
2106 channel->curr_ier |= channel->saved_ier; in xgbe_enable_int()
2109 return -1; in xgbe_enable_int()
2112 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_int()
2122 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
2125 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); in xgbe_disable_int()
2128 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); in xgbe_disable_int()
2131 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
2134 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); in xgbe_disable_int()
2137 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); in xgbe_disable_int()
2140 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
2141 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
2144 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); in xgbe_disable_int()
2147 channel->saved_ier = channel->curr_ier; in xgbe_disable_int()
2148 channel->curr_ier = 0; in xgbe_disable_int()
2151 return -1; in xgbe_disable_int()
2154 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_disable_int()
2163 DBGPR("-->xgbe_exit\n"); in __xgbe_exit()
2170 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
2174 return -EBUSY; in __xgbe_exit()
2176 DBGPR("<--xgbe_exit\n"); in __xgbe_exit()
2199 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
2202 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
2206 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
2208 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
2213 return -EBUSY; in xgbe_flush_tx_queues()
2228 /* Set the System Bus mode */ in xgbe_config_dma_bus()
2230 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
2231 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
2232 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
2233 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
2238 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
2240 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
2242 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
2244 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
2249 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
2250 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
2251 if (pdata->awarcr) in xgbe_config_dma_cache()
2252 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
2263 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
2282 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { in xgbe_queue_flow_control_threshold()
2284 rfa = pdata->pfc_rfa; in xgbe_queue_flow_control_threshold()
2289 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; in xgbe_queue_flow_control_threshold()
2298 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
2299 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
2305 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
2306 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
2311 /* Between 4096 and max-frame */ in xgbe_queue_flow_control_threshold()
2312 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
2313 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
2318 /* Between max-frame and 3 max-frames, in xgbe_queue_flow_control_threshold()
2322 rfa = q_fifo_size - frame_fifo_size; in xgbe_queue_flow_control_threshold()
2325 /* Above 3 max-frames - trigger when just over in xgbe_queue_flow_control_threshold()
2334 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
2335 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
2344 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
2355 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
2357 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
2359 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
2366 return min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
2367 pdata->hw_feat.tx_fifo_size); in xgbe_get_tx_fifo_size()
2373 return min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
2374 pdata->hw_feat.rx_fifo_size); in xgbe_get_rx_fifo_size()
2393 p_fifo--; in xgbe_calculate_equal_fifo()
2416 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; in xgbe_set_nonprio_fifos()
2417 fifo_size -= XGMAC_FIFO_MIN_ALLOC; in xgbe_set_nonprio_fifos()
2428 if (pdata->pfc->delay) in xgbe_get_pfc_delay()
2429 return pdata->pfc->delay / 8; in xgbe_get_pfc_delay()
2452 if (!pdata->pfc->pfc_en) in xgbe_get_pfc_queues()
2456 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_get_pfc_queues()
2461 pdata->pfcq[i] = 1; in xgbe_get_pfc_queues()
2478 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_calculate_dcb_fifo()
2488 rem_fifo = fifo_size - (q_fifo_size * prio_queues); in xgbe_calculate_dcb_fifo()
2493 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); in xgbe_calculate_dcb_fifo()
2494 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); in xgbe_calculate_dcb_fifo()
2496 if (pdata->pfc_rfa > q_fifo_size) { in xgbe_calculate_dcb_fifo()
2497 addn_fifo = pdata->pfc_rfa - q_fifo_size; in xgbe_calculate_dcb_fifo()
2504 * - distribute remaining fifo between the VLAN priority in xgbe_calculate_dcb_fifo()
2510 i--; in xgbe_calculate_dcb_fifo()
2512 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; in xgbe_calculate_dcb_fifo()
2514 if (!pdata->pfcq[i] || !addn_fifo) in xgbe_calculate_dcb_fifo()
2518 netdev_warn(pdata->netdev, in xgbe_calculate_dcb_fifo()
2527 rem_fifo -= addn_fifo; in xgbe_calculate_dcb_fifo()
2547 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
2549 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_fifo_size()
2552 netif_info(pdata, drv, pdata->netdev, in xgbe_config_tx_fifo_size()
2554 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
2565 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); in xgbe_config_rx_fifo_size()
2566 pdata->pfc_rfa = 0; in xgbe_config_rx_fifo_size()
2569 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2571 /* Assign a minimum fifo to the non-VLAN priority queues */ in xgbe_config_rx_fifo_size()
2572 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
2574 if (pdata->pfc && pdata->ets) in xgbe_config_rx_fifo_size()
2579 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2585 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { in xgbe_config_rx_fifo_size()
2586 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2587 "%u Rx hardware queues\n", pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2588 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2589 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2593 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2595 pdata->rx_q_count, in xgbe_config_rx_fifo_size()
2611 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2612 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2614 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
2616 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2620 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2624 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2628 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2633 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
2642 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2645 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2649 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2652 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2668 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2671 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2686 netdev_reset_tc(pdata->netdev); in xgbe_config_tc()
2687 if (!pdata->num_tcs) in xgbe_config_tc()
2690 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); in xgbe_config_tc()
2692 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { in xgbe_config_tc()
2693 while ((queue < pdata->tx_q_count) && in xgbe_config_tc()
2694 (pdata->q2tc_map[queue] == i)) in xgbe_config_tc()
2697 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", in xgbe_config_tc()
2698 i, offset, queue - 1); in xgbe_config_tc()
2699 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); in xgbe_config_tc()
2703 if (!pdata->ets) in xgbe_config_tc()
2707 netdev_set_prio_tc_map(pdata->netdev, prio, in xgbe_config_tc()
2708 pdata->ets->prio_tc[prio]); in xgbe_config_tc()
2713 struct ieee_ets *ets = pdata->ets; in xgbe_config_dcb_tc()
2727 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; in xgbe_config_dcb_tc()
2732 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_dcb_tc()
2736 if (ets->prio_tc[prio] == i) in xgbe_config_dcb_tc()
2741 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", in xgbe_config_dcb_tc()
2752 switch (ets->tc_tsa[i]) { in xgbe_config_dcb_tc()
2754 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2760 weight = total_weight * ets->tc_tx_bw[i] / 100; in xgbe_config_dcb_tc()
2763 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2778 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2780 netif_tx_stop_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2783 pdata->hw_if.disable_rx(pdata); in xgbe_config_dcb_pfc()
2789 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2791 pdata->hw_if.enable_rx(pdata); in xgbe_config_dcb_pfc()
2794 netif_tx_start_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2800 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); in xgbe_config_mac_address()
2803 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2814 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2821 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2826 if (pdata->netdev->features & NETIF_F_RXCSUM) in xgbe_config_checksum_offload()
2841 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_config_vlan_support()
2846 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) in xgbe_config_vlan_support()
2857 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2896 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2900 stats->txoctetcount_gb += in xgbe_tx_mmc_int()
2904 stats->txframecount_gb += in xgbe_tx_mmc_int()
2908 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2912 stats->txmulticastframes_g += in xgbe_tx_mmc_int()
2916 stats->tx64octets_gb += in xgbe_tx_mmc_int()
2920 stats->tx65to127octets_gb += in xgbe_tx_mmc_int()
2924 stats->tx128to255octets_gb += in xgbe_tx_mmc_int()
2928 stats->tx256to511octets_gb += in xgbe_tx_mmc_int()
2932 stats->tx512to1023octets_gb += in xgbe_tx_mmc_int()
2936 stats->tx1024tomaxoctets_gb += in xgbe_tx_mmc_int()
2940 stats->txunicastframes_gb += in xgbe_tx_mmc_int()
2944 stats->txmulticastframes_gb += in xgbe_tx_mmc_int()
2948 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2952 stats->txunderflowerror += in xgbe_tx_mmc_int()
2956 stats->txoctetcount_g += in xgbe_tx_mmc_int()
2960 stats->txframecount_g += in xgbe_tx_mmc_int()
2964 stats->txpauseframes += in xgbe_tx_mmc_int()
2968 stats->txvlanframes_g += in xgbe_tx_mmc_int()
2974 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2978 stats->rxframecount_gb += in xgbe_rx_mmc_int()
2982 stats->rxoctetcount_gb += in xgbe_rx_mmc_int()
2986 stats->rxoctetcount_g += in xgbe_rx_mmc_int()
2990 stats->rxbroadcastframes_g += in xgbe_rx_mmc_int()
2994 stats->rxmulticastframes_g += in xgbe_rx_mmc_int()
2998 stats->rxcrcerror += in xgbe_rx_mmc_int()
3002 stats->rxrunterror += in xgbe_rx_mmc_int()
3006 stats->rxjabbererror += in xgbe_rx_mmc_int()
3010 stats->rxundersize_g += in xgbe_rx_mmc_int()
3014 stats->rxoversize_g += in xgbe_rx_mmc_int()
3018 stats->rx64octets_gb += in xgbe_rx_mmc_int()
3022 stats->rx65to127octets_gb += in xgbe_rx_mmc_int()
3026 stats->rx128to255octets_gb += in xgbe_rx_mmc_int()
3030 stats->rx256to511octets_gb += in xgbe_rx_mmc_int()
3034 stats->rx512to1023octets_gb += in xgbe_rx_mmc_int()
3038 stats->rx1024tomaxoctets_gb += in xgbe_rx_mmc_int()
3042 stats->rxunicastframes_g += in xgbe_rx_mmc_int()
3046 stats->rxlengtherror += in xgbe_rx_mmc_int()
3050 stats->rxoutofrangetype += in xgbe_rx_mmc_int()
3054 stats->rxpauseframes += in xgbe_rx_mmc_int()
3058 stats->rxfifooverflow += in xgbe_rx_mmc_int()
3062 stats->rxvlanframes_gb += in xgbe_rx_mmc_int()
3066 stats->rxwatchdogerror += in xgbe_rx_mmc_int()
3072 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
3077 stats->txoctetcount_gb += in xgbe_read_mmc_stats()
3080 stats->txframecount_gb += in xgbe_read_mmc_stats()
3083 stats->txbroadcastframes_g += in xgbe_read_mmc_stats()
3086 stats->txmulticastframes_g += in xgbe_read_mmc_stats()
3089 stats->tx64octets_gb += in xgbe_read_mmc_stats()
3092 stats->tx65to127octets_gb += in xgbe_read_mmc_stats()
3095 stats->tx128to255octets_gb += in xgbe_read_mmc_stats()
3098 stats->tx256to511octets_gb += in xgbe_read_mmc_stats()
3101 stats->tx512to1023octets_gb += in xgbe_read_mmc_stats()
3104 stats->tx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
3107 stats->txunicastframes_gb += in xgbe_read_mmc_stats()
3110 stats->txmulticastframes_gb += in xgbe_read_mmc_stats()
3113 stats->txbroadcastframes_g += in xgbe_read_mmc_stats()
3116 stats->txunderflowerror += in xgbe_read_mmc_stats()
3119 stats->txoctetcount_g += in xgbe_read_mmc_stats()
3122 stats->txframecount_g += in xgbe_read_mmc_stats()
3125 stats->txpauseframes += in xgbe_read_mmc_stats()
3128 stats->txvlanframes_g += in xgbe_read_mmc_stats()
3131 stats->rxframecount_gb += in xgbe_read_mmc_stats()
3134 stats->rxoctetcount_gb += in xgbe_read_mmc_stats()
3137 stats->rxoctetcount_g += in xgbe_read_mmc_stats()
3140 stats->rxbroadcastframes_g += in xgbe_read_mmc_stats()
3143 stats->rxmulticastframes_g += in xgbe_read_mmc_stats()
3146 stats->rxcrcerror += in xgbe_read_mmc_stats()
3149 stats->rxrunterror += in xgbe_read_mmc_stats()
3152 stats->rxjabbererror += in xgbe_read_mmc_stats()
3155 stats->rxundersize_g += in xgbe_read_mmc_stats()
3158 stats->rxoversize_g += in xgbe_read_mmc_stats()
3161 stats->rx64octets_gb += in xgbe_read_mmc_stats()
3164 stats->rx65to127octets_gb += in xgbe_read_mmc_stats()
3167 stats->rx128to255octets_gb += in xgbe_read_mmc_stats()
3170 stats->rx256to511octets_gb += in xgbe_read_mmc_stats()
3173 stats->rx512to1023octets_gb += in xgbe_read_mmc_stats()
3176 stats->rx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
3179 stats->rxunicastframes_g += in xgbe_read_mmc_stats()
3182 stats->rxlengtherror += in xgbe_read_mmc_stats()
3185 stats->rxoutofrangetype += in xgbe_read_mmc_stats()
3188 stats->rxpauseframes += in xgbe_read_mmc_stats()
3191 stats->rxfifooverflow += in xgbe_read_mmc_stats()
3194 stats->rxvlanframes_gb += in xgbe_read_mmc_stats()
3197 stats->rxwatchdogerror += in xgbe_read_mmc_stats()
3200 /* Un-freeze counters */ in xgbe_read_mmc_stats()
3234 netdev_info(pdata->netdev, in xgbe_txq_prepare_tx_stop()
3246 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
3254 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; in xgbe_prepare_tx_stop()
3277 netdev_info(pdata->netdev, in xgbe_prepare_tx_stop()
3287 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
3288 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
3291 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
3295 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
3308 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3315 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3319 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
3320 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
3323 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
3348 netdev_info(pdata->netdev, in xgbe_prepare_rx_stop()
3358 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
3359 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
3362 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
3367 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
3389 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
3396 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
3397 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
3400 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
3409 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
3410 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
3413 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
3425 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
3432 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
3433 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
3436 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
3445 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
3446 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
3449 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
3458 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
3459 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
3462 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
3468 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
3471 DBGPR("-->xgbe_init\n"); in xgbe_init()
3476 netdev_err(pdata->netdev, "error flushing TX queues\n"); in xgbe_init()
3493 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
3494 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
3502 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
3503 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
3504 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
3505 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
3532 DBGPR("<--xgbe_init\n"); in xgbe_init()
3539 DBGPR("-->xgbe_init_function_ptrs\n"); in xgbe_init_function_ptrs_dev()
3541 hw_if->tx_complete = xgbe_tx_complete; in xgbe_init_function_ptrs_dev()
3543 hw_if->set_mac_address = xgbe_set_mac_address; in xgbe_init_function_ptrs_dev()
3544 hw_if->config_rx_mode = xgbe_config_rx_mode; in xgbe_init_function_ptrs_dev()
3546 hw_if->enable_rx_csum = xgbe_enable_rx_csum; in xgbe_init_function_ptrs_dev()
3547 hw_if->disable_rx_csum = xgbe_disable_rx_csum; in xgbe_init_function_ptrs_dev()
3549 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
3550 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
3551 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
3552 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
3553 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; in xgbe_init_function_ptrs_dev()
3555 hw_if->read_mmd_regs = xgbe_read_mmd_regs; in xgbe_init_function_ptrs_dev()
3556 hw_if->write_mmd_regs = xgbe_write_mmd_regs; in xgbe_init_function_ptrs_dev()
3558 hw_if->set_speed = xgbe_set_speed; in xgbe_init_function_ptrs_dev()
3560 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; in xgbe_init_function_ptrs_dev()
3561 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; in xgbe_init_function_ptrs_dev()
3562 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; in xgbe_init_function_ptrs_dev()
3564 hw_if->set_gpio = xgbe_set_gpio; in xgbe_init_function_ptrs_dev()
3565 hw_if->clr_gpio = xgbe_clr_gpio; in xgbe_init_function_ptrs_dev()
3567 hw_if->enable_tx = xgbe_enable_tx; in xgbe_init_function_ptrs_dev()
3568 hw_if->disable_tx = xgbe_disable_tx; in xgbe_init_function_ptrs_dev()
3569 hw_if->enable_rx = xgbe_enable_rx; in xgbe_init_function_ptrs_dev()
3570 hw_if->disable_rx = xgbe_disable_rx; in xgbe_init_function_ptrs_dev()
3572 hw_if->powerup_tx = xgbe_powerup_tx; in xgbe_init_function_ptrs_dev()
3573 hw_if->powerdown_tx = xgbe_powerdown_tx; in xgbe_init_function_ptrs_dev()
3574 hw_if->powerup_rx = xgbe_powerup_rx; in xgbe_init_function_ptrs_dev()
3575 hw_if->powerdown_rx = xgbe_powerdown_rx; in xgbe_init_function_ptrs_dev()
3577 hw_if->dev_xmit = xgbe_dev_xmit; in xgbe_init_function_ptrs_dev()
3578 hw_if->dev_read = xgbe_dev_read; in xgbe_init_function_ptrs_dev()
3579 hw_if->enable_int = xgbe_enable_int; in xgbe_init_function_ptrs_dev()
3580 hw_if->disable_int = xgbe_disable_int; in xgbe_init_function_ptrs_dev()
3581 hw_if->init = xgbe_init; in xgbe_init_function_ptrs_dev()
3582 hw_if->exit = xgbe_exit; in xgbe_init_function_ptrs_dev()
3585 hw_if->tx_desc_init = xgbe_tx_desc_init; in xgbe_init_function_ptrs_dev()
3586 hw_if->rx_desc_init = xgbe_rx_desc_init; in xgbe_init_function_ptrs_dev()
3587 hw_if->tx_desc_reset = xgbe_tx_desc_reset; in xgbe_init_function_ptrs_dev()
3588 hw_if->rx_desc_reset = xgbe_rx_desc_reset; in xgbe_init_function_ptrs_dev()
3589 hw_if->is_last_desc = xgbe_is_last_desc; in xgbe_init_function_ptrs_dev()
3590 hw_if->is_context_desc = xgbe_is_context_desc; in xgbe_init_function_ptrs_dev()
3591 hw_if->tx_start_xmit = xgbe_tx_start_xmit; in xgbe_init_function_ptrs_dev()
3594 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; in xgbe_init_function_ptrs_dev()
3595 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; in xgbe_init_function_ptrs_dev()
3598 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; in xgbe_init_function_ptrs_dev()
3599 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; in xgbe_init_function_ptrs_dev()
3600 hw_if->usec_to_riwt = xgbe_usec_to_riwt; in xgbe_init_function_ptrs_dev()
3601 hw_if->riwt_to_usec = xgbe_riwt_to_usec; in xgbe_init_function_ptrs_dev()
3604 hw_if->config_rx_threshold = xgbe_config_rx_threshold; in xgbe_init_function_ptrs_dev()
3605 hw_if->config_tx_threshold = xgbe_config_tx_threshold; in xgbe_init_function_ptrs_dev()
3608 hw_if->config_rsf_mode = xgbe_config_rsf_mode; in xgbe_init_function_ptrs_dev()
3609 hw_if->config_tsf_mode = xgbe_config_tsf_mode; in xgbe_init_function_ptrs_dev()
3612 hw_if->config_osp_mode = xgbe_config_osp_mode; in xgbe_init_function_ptrs_dev()
3615 hw_if->tx_mmc_int = xgbe_tx_mmc_int; in xgbe_init_function_ptrs_dev()
3616 hw_if->rx_mmc_int = xgbe_rx_mmc_int; in xgbe_init_function_ptrs_dev()
3617 hw_if->read_mmc_stats = xgbe_read_mmc_stats; in xgbe_init_function_ptrs_dev()
3620 hw_if->config_tstamp = xgbe_config_tstamp; in xgbe_init_function_ptrs_dev()
3621 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; in xgbe_init_function_ptrs_dev()
3622 hw_if->set_tstamp_time = xgbe_set_tstamp_time; in xgbe_init_function_ptrs_dev()
3623 hw_if->get_tstamp_time = xgbe_get_tstamp_time; in xgbe_init_function_ptrs_dev()
3624 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; in xgbe_init_function_ptrs_dev()
3627 hw_if->config_tc = xgbe_config_tc; in xgbe_init_function_ptrs_dev()
3628 hw_if->config_dcb_tc = xgbe_config_dcb_tc; in xgbe_init_function_ptrs_dev()
3629 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; in xgbe_init_function_ptrs_dev()
3632 hw_if->enable_rss = xgbe_enable_rss; in xgbe_init_function_ptrs_dev()
3633 hw_if->disable_rss = xgbe_disable_rss; in xgbe_init_function_ptrs_dev()
3634 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; in xgbe_init_function_ptrs_dev()
3635 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; in xgbe_init_function_ptrs_dev()
3638 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; in xgbe_init_function_ptrs_dev()
3639 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; in xgbe_init_function_ptrs_dev()
3642 hw_if->enable_vxlan = xgbe_enable_vxlan; in xgbe_init_function_ptrs_dev()
3643 hw_if->disable_vxlan = xgbe_disable_vxlan; in xgbe_init_function_ptrs_dev()
3644 hw_if->set_vxlan_id = xgbe_set_vxlan_id; in xgbe_init_function_ptrs_dev()
3646 DBGPR("<--xgbe_init_function_ptrs\n"); in xgbe_init_function_ptrs_dev()