Lines Matching refs:writereg
159 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
166 #define writedatareg(val) { writereg(val,CSR0); }
169 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} macro
171 #define writedatareg(val) { writereg(val,CSR0); }
273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ in ni65_set_performance()
282 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */ in ni65_set_performance()
535 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()
574 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); in ni65_init_lance()
585 writereg(0,CSR3); /* busmaster/no word-swap */ in ni65_init_lance()
587 writereg(pib & 0xffff,CSR1); in ni65_init_lance()
588 writereg(pib >> 16,CSR2); in ni65_init_lance()
590 writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */ in ni65_init_lance()