Lines Matching +full:poll +full:- +full:retry +full:- +full:count
4 * © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
8 * ----------------------------------------------------------------------------------
13 * Written 1993-94 by Donald Becker.
15 * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
22 * ----------------------------------------------------------------------------------
28 * ----------------------------------------------------------------------------------
30 * The Ariadne is a Zorro-II board made by Village Tronic. It contains:
32 * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
33 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
35 * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
40 * Am79C960 PCnet-ISA
58 * Only registers marked with a `-' are intended for network software
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
71 #define CSR11 0x0b00 /* - Logical Address Filter, LADRF[63:48] */
72 #define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */
73 #define CSR13 0x0d00 /* - Physical Address Register, PADR[31:16] */
74 #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */
75 #define CSR15 0x0f00 /* - Mode Register */
84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
90 #define CSR30 0x1e00 /* - Base Address of Transmit Ring */
91 #define CSR31 0x1f00 /* - Base Address of transmit Ring */
100 #define CSR40 0x2800 /* Current Receive Status and Byte Count */
101 #define CSR41 0x2900 /* Current Receive Status and Byte Count */
102 #define CSR42 0x2a00 /* Current Transmit Status and Byte Count */
103 #define CSR43 0x2b00 /* Current Transmit Status and Byte Count */
104 #define CSR44 0x2c00 /* Next Receive Status and Byte Count */
105 #define CSR45 0x2d00 /* Next Receive Status and Byte Count */
106 #define CSR46 0x2e00 /* Poll Time Counter */
122 #define CSR62 0x3e00 /* Previous Transmit Status and Byte Count */
123 #define CSR63 0x3f00 /* Previous Transmit Status and Byte Count */
126 #define CSR66 0x4200 /* Next Transmit Status and Byte Count */
127 #define CSR67 0x4300 /* Next Transmit Status and Byte Count */
134 #define CSR76 0x4c00 /* - Receive Ring Length */
135 #define CSR78 0x4e00 /* - Transmit Ring Length */
136 #define CSR80 0x5000 /* - Burst and FIFO Threshold Control */
137 #define CSR82 0x5200 /* - Bus Activity Timer */
141 #define CSR88 0x5800 /* - Chip ID */
142 #define CSR89 0x5900 /* - Chip ID */
144 #define CSR94 0x5e00 /* Transmit Time Domain Reflectometry Count */
153 #define CSR112 0x7000 /* - Missed Frame Count */
154 #define CSR114 0x7200 /* - Receive Collision Count */
155 #define CSR124 0x7c00 /* - Buffer Management Unit Test */
174 * Bit definitions for CSR0 (PCnet-ISA Controller Status)
181 #define CERR 0x0020 /* No Heartbeat (10BASE-T) */
210 #define EMBA 0x0800 /* Enable Modified Back-off Algorithm */
251 #define DRTY 0x2000 /* Disable Retry */
269 * Bit definitions for ISACSR5-7 (LED1-3 Status)
290 volatile u_short RMD2; /* Buffer Byte Count (two's complement) */
291 volatile u_short RMD3; /* Message Byte Count */
302 volatile u_short TMD2; /* Buffer Byte Count (two's complement) */
311 #define RF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
325 #define TF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
328 #define TF_MORE 0x0010 /* More than one retry needed */
329 #define TF_ONE 0x0008 /* One retry needed */
343 #define EF_RTRY 0x0004 /* Retry Error */
391 volatile u_char CNTRH; /* Count Register (High) */
393 volatile u_char CNTRM; /* Count Register (Mid) */
395 volatile u_char CNTRL; /* Count Register (Low) */
410 #define ARIADNE_BOOTPROM 0x4000 /* I guess it's here :-) */