Lines Matching +full:0 +full:xf
20 3.0.0
32 … 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits w…
39 #define ASF_STAT 0x00 /* ASF status register */
40 #define CHIPID 0x04 /* Chip ID register */
41 #define MIB_DATA 0x10 /* MIB data register */
42 #define MIB_ADDR 0x14 /* MIB address register */
43 #define STAT0 0x30 /* Status0 register */
44 #define INT0 0x38 /* Interrupt0 register */
45 #define INTEN0 0x40 /* Interrupt0 enable register*/
46 #define CMD0 0x48 /* Command0 register */
47 #define CMD2 0x50 /* Command2 register */
48 #define CMD3 0x54 /* Command3 resiter */
49 #define CMD7 0x64 /* Command7 register */
51 #define CTRL1 0x6C /* Control1 register */
52 #define CTRL2 0x70 /* Control2 register */
54 #define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */
56 #define AUTOPOLL0 0x88 /* Auto-poll0 register */
57 #define AUTOPOLL1 0x8A /* Auto-poll1 register */
58 #define AUTOPOLL2 0x8C /* Auto-poll2 register */
59 #define AUTOPOLL3 0x8E /* Auto-poll3 register */
60 #define AUTOPOLL4 0x90 /* Auto-poll4 register */
61 #define AUTOPOLL5 0x92 /* Auto-poll5 register */
63 #define AP_VALUE 0x98 /* Auto-poll value register */
64 #define DLY_INT_A 0xA8 /* Group A delayed interrupt register */
65 #define DLY_INT_B 0xAC /* Group B delayed interrupt register */
67 #define FLOW_CONTROL 0xC8 /* Flow control register */
68 #define PHY_ACCESS 0xD0 /* PHY access register */
70 #define STVAL 0xD8 /* Software timer value register */
72 #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */
73 #define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */
74 #define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */
75 #define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */
77 #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */
79 #define PMAT0 0x190 /* OnNow pattern register0 */
80 #define PMAT1 0x194 /* OnNow pattern register1 */
84 #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */
85 #define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */
86 #define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */
87 #define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */
89 #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */
91 #define SRAM_SIZE 0x178 /* SRAM size register */
92 #define SRAM_BOUNDARY 0x17A /* SRAM boundary register */
96 #define PADR 0x160 /* Physical address register */
98 #define IFS1 0x18C /* Inter-frame spacing Part1 register */
99 #define IFS 0x18D /* Inter-frame spacing register */
100 #define IPG 0x18E /* Inter-frame gap register */
103 #define LADRF 0x168 /* Logical address filter register */
110 ASF_INIT_PRESENT = (1 << 0),
119 MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
136 RUNNING = (1 << 0),
140 #define PHY_SPEED_10 0x2
141 #define PHY_SPEED_100 0x3
143 /* INT0 0x38, 32bit register */
169 RINT0 = (1 << 0),
178 VAL0 = (1 << 7), /* VAL bit for byte 0 */
207 RINTEN0 = (1 << 0),
209 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
228 RUN = (1 << 0),
230 CMD0_CLEAR = 0x000F0F7F, /* Command style register */
257 REX_LCOL = (1 << 0),
259 CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
282 PHY_RST_POL = (1 << 0),
293 LCMODE_SW = (1 << 0),
295 CMD7_CLEAR = 0x0000001B /* Command style register */
302 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
307 BURST_LIMIT_MASK = (0xF << 0 ),
308 CTRL1_DEFAULT = 0x00010111,
319 APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
323 /* XMT_RING_LIMIT 0x7C, 32bit register */
326 XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */
327 XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */
328 XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */
335 AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
336 AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
340 /* AUTOPOLL1 0x8A, 16bit register */
344 AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
347 AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
355 AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
358 AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
365 AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
368 AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
376 AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
379 AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
387 AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
390 AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
397 /* AP_VALUE 0x98, 32bit ragister */
403 AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
404 (0xF << 12), /* 15:0 */
418 EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */
419 MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
420 (1 << 9) | (1 << 10), /* 10:0 */
434 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
435 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
436 (1 << 9) | (1 << 10), /* 10:0 */
440 /* FLOW_CONTROL 0xC8, 32bit register */
450 PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */
454 /* PHY_ ACCESS 0xD0, 32bit register */
465 PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
466 (0xF << 12),/* 15:0 */
471 /* PMAT0 0x190, 32bit register */
477 PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
479 PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */
483 /* PMAT1 0x194, 32bit register */
485 PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */
486 PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */
487 PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */
488 PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
497 #define rcv_miss_pkts 0x00
498 #define rcv_octets 0x01
499 #define rcv_broadcast_pkts 0x02
500 #define rcv_multicast_pkts 0x03
501 #define rcv_undersize_pkts 0x04
502 #define rcv_oversize_pkts 0x05
503 #define rcv_fragments 0x06
504 #define rcv_jabbers 0x07
505 #define rcv_unicast_pkts 0x08
506 #define rcv_alignment_errors 0x09
507 #define rcv_fcs_errors 0x0A
508 #define rcv_good_octets 0x0B
509 #define rcv_mac_ctrl 0x0C
510 #define rcv_flow_ctrl 0x0D
511 #define rcv_pkts_64_octets 0x0E
512 #define rcv_pkts_65to127_octets 0x0F
513 #define rcv_pkts_128to255_octets 0x10
514 #define rcv_pkts_256to511_octets 0x11
515 #define rcv_pkts_512to1023_octets 0x12
516 #define rcv_pkts_1024to1518_octets 0x13
517 #define rcv_unsupported_opcode 0x14
518 #define rcv_symbol_errors 0x15
519 #define rcv_drop_pkts_ring1 0x16
520 #define rcv_drop_pkts_ring2 0x17
521 #define rcv_drop_pkts_ring3 0x18
522 #define rcv_drop_pkts_ring4 0x19
523 #define rcv_jumbo_pkts 0x1A
525 #define xmt_underrun_pkts 0x20
526 #define xmt_octets 0x21
527 #define xmt_packets 0x22
528 #define xmt_broadcast_pkts 0x23
529 #define xmt_multicast_pkts 0x24
530 #define xmt_collisions 0x25
531 #define xmt_unicast_pkts 0x26
532 #define xmt_one_collision 0x27
533 #define xmt_multiple_collision 0x28
534 #define xmt_deferred_transmit 0x29
535 #define xmt_late_collision 0x2A
536 #define xmt_excessive_defer 0x2B
537 #define xmt_loss_carrier 0x2C
538 #define xmt_excessive_collision 0x2D
539 #define xmt_back_pressure 0x2E
540 #define xmt_flow_ctrl 0x2F
541 #define xmt_pkts_64_octets 0x30
542 #define xmt_pkts_65to127_octets 0x31
543 #define xmt_pkts_128to255_octets 0x32
544 #define xmt_pkts_256to511_octets 0x33
545 #define xmt_pkts_512to1023_octets 0x34
546 #define xmt_pkts_1024to1518_octet 0x35
547 #define xmt_oversize_pkts 0x36
548 #define xmt_jumbo_pkts 0x37
553 #define PCI_VENDOR_ID_AMD 0x1022
554 #define PCI_DEVICE_ID_AMD8111E_7462 0x7462
578 #define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */
581 #define OPTION_VLAN_ENABLE 0x0001
582 #define OPTION_JUMBO_ENABLE 0x0002
583 #define OPTION_MULTICAST_ENABLE 0x0004
584 #define OPTION_WOL_ENABLE 0x0008
585 #define OPTION_WAKE_MAGIC_ENABLE 0x0010
586 #define OPTION_WAKE_PHY_ENABLE 0x0020
587 #define OPTION_INTR_COAL_ENABLE 0x0040
588 #define OPTION_DYN_IPG_ENABLE 0x0080
590 #define PHY_REG_ADDR_MASK 0x1f
593 #define DEFAULT_IPG 0x60
616 TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
628 TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */
629 TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */
633 #define RESET_RX_FLAGS 0x0000
634 #define TT_MASK 0x000c
635 #define TCC_MASK 0x0003
674 #define SPEED_INVALID 0xffff
675 #define DUPLEX_INVALID 0xff
676 #define AUTONEG_INVALID 0xff
796 static int speed_duplex[MAX_UNITS] = { 0, };
797 static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
798 static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };