Lines Matching +full:rx +full:- +full:tx +full:- +full:swap

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * 7990.h -- LANCE ethernet IC generic routines.
11  * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
25  * reorder queued Tx packets based on priority. [Clearly there is a minimum
26  * limit too: too small and we drop rx packets and can't tx at full speed.]
32  * too long (and overflow the RAM on shared-memory cards like the HP LANCE.
41 #define TX_RING_MOD_MASK	(TX_RING_SIZE - 1)
42 #define RX_RING_MOD_MASK	(RX_RING_SIZE - 1)
71  * init block,the Tx and Rx rings and the buffers together in memory:
74 	volatile unsigned short mode;		/* Pre-set mode (reg. 15) */
84 	/* The Tx and Rx ring entries must be aligned on 8-byte boundaries.
85 	 * This will be true if this whole struct is 8-byte aligned.
114 	int auto_select;		/* cable-selection is by carrier */
120 	 * a DIO-specific register every time you read/write the LANCE regs :-<
143 #define LE_C0_CERR	0x2000	/* No Heartbeat (10BASE-T) */
144 #define LE_C0_MISS	0x1000	/* Missed Frame (no rx buffer to put it in) */
163 #define LE_C3_BSWP	0x0004	/* Byte Swap (on for big endian byte order) */
172 /* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
173  * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips
180 #define LE_MO_LRTTSEL	0x0200	/* lower RX threshold / TX mode selection */
183 /* and this one is from the C-LANCE data sheet... */
185 				   (C-LANCE, not original LANCE) */
234 #define TX_BUFFS_AVAIL ((lp->tx_old <= lp->tx_new) ? \
235 			lp->tx_old + lp->tx_ring_mod_mask - lp->tx_new : \
236 			lp->tx_old - lp->tx_new - 1)