148 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);  in ena_com_admin_init_aenq()
149 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);  in ena_com_admin_init_aenq()
156 	writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);  in ena_com_admin_init_aenq()
816 		return readl(ena_dev->reg_bar + offset);  in ena_com_reg_bar_read32()
827 	writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);  in ena_com_reg_bar_read32()
1243 	io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_sq()
1384 	io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1389 			(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1394 			(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1503 	writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_admin_aenq_enable()
1667 	writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);  in ena_com_set_admin_polling_mode()
1713 	writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_destroy()
1714 	writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_destroy()
1730 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1731 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1775 	admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_admin_init()
1781 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);  in ena_com_admin_init()
1782 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);  in ena_com_admin_init()
1787 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);  in ena_com_admin_init()
1788 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);  in ena_com_admin_init()
1802 	writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);  in ena_com_admin_init()
1803 	writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);  in ena_com_admin_init()
2068 		       ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_aenq_intr_handler()
2102 	writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()
2115 	writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()