Lines Matching +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken
1 // SPDX-License-Identifier: GPL-2.0-only
69 static int
70 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) in core_read_mmd_indirect()
72 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
73 int value, ret; in core_read_mmd_indirect()
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
91 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
95 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
100 static int
101 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, in core_write_mmd_indirect()
102 int devad, u32 data) in core_write_mmd_indirect()
104 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
105 int ret; in core_write_mmd_indirect()
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
123 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
126 dev_err(&bus->dev, in core_write_mmd_indirect()
134 struct mii_bus *bus = priv->bus; in core_write()
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_write()
140 mutex_unlock(&bus->mdio_lock); in core_write()
146 struct mii_bus *bus = priv->bus; in core_rmw()
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_rmw()
156 mutex_unlock(&bus->mdio_lock); in core_rmw()
171 static int
174 struct mii_bus *bus = priv->bus; in mt7530_mii_write()
176 int ret; in mt7530_mii_write()
184 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_write()
188 ret = bus->write(bus, 0x1f, r, lo); in mt7530_mii_write()
192 ret = bus->write(bus, 0x1f, 0x10, hi); in mt7530_mii_write()
195 dev_err(&bus->dev, in mt7530_mii_write()
203 struct mii_bus *bus = priv->bus; in mt7530_mii_read()
205 int ret; in mt7530_mii_read()
211 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_read()
213 dev_err(&bus->dev, in mt7530_mii_read()
218 lo = bus->read(bus, 0x1f, r); in mt7530_mii_read()
219 hi = bus->read(bus, 0x1f, 0x10); in mt7530_mii_read()
227 struct mii_bus *bus = priv->bus; in mt7530_write()
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_write()
233 mutex_unlock(&bus->mdio_lock); in mt7530_write()
239 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
245 struct mii_bus *bus = p->priv->bus; in _mt7530_read()
248 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in _mt7530_read()
250 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
252 mutex_unlock(&bus->mdio_lock); in _mt7530_read()
270 struct mii_bus *bus = priv->bus; in mt7530_rmw()
273 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_rmw()
280 mutex_unlock(&bus->mdio_lock); in mt7530_rmw()
295 static int
299 int ret; in mt7530_fdb_cmd()
310 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
319 return -EINVAL; in mt7530_fdb_cmd()
331 int i; in mt7530_fdb_read()
337 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
341 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
342 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
343 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
344 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
345 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
346 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
347 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
348 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
349 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
350 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
359 int i; in mt7530_fdb_write()
382 static int
385 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
391 dev_err(priv->dev, in mt7530_pad_clk_setup()
394 return -EINVAL; in mt7530_pad_clk_setup()
405 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
419 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
421 return -EINVAL; in mt7530_pad_clk_setup()
437 /* Setup core clock for MT7530 */ in mt7530_pad_clk_setup()
439 /* Disable MT7530 core clock */ in mt7530_pad_clk_setup()
452 /* Set core clock into 500Mhz */ in mt7530_pad_clk_setup()
463 /* Enable MT7530 core clock */ in mt7530_pad_clk_setup()
467 /* Setup the MT7530 TRGMII Tx Clock */ in mt7530_pad_clk_setup()
501 static int
504 struct mt7530_priv *priv = ds->priv; in mt7531_pad_setup()
575 /* Enable 325M clock for SGMII */ in mt7531_pad_setup()
578 /* Enable 250SSC clock for RGMII */ in mt7531_pad_setup()
597 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
603 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) in mt7530_phy_read()
605 struct mt7530_priv *priv = ds->priv; in mt7530_phy_read()
607 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read()
610 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, in mt7530_phy_write()
613 struct mt7530_priv *priv = ds->priv; in mt7530_phy_write()
615 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write()
618 static int
619 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_read()
620 int regnum) in mt7531_ind_c45_phy_read()
622 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_read()
625 int ret; in mt7531_ind_c45_phy_read()
629 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_read()
634 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
645 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
656 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
662 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_read()
667 static int
668 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_write()
669 int regnum, u32 data) in mt7531_ind_c45_phy_write()
671 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_write()
674 int ret; in mt7531_ind_c45_phy_write()
678 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_write()
683 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
694 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
705 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
710 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_write()
715 static int
716 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) in mt7531_ind_c22_phy_read()
718 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_read()
720 int ret; in mt7531_ind_c22_phy_read()
725 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_read()
730 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
742 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
748 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_read()
753 static int
754 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, in mt7531_ind_c22_phy_write()
757 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_write()
759 int ret; in mt7531_ind_c22_phy_write()
764 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_write()
769 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
781 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
786 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_write()
791 static int
792 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) in mt7531_ind_phy_read()
794 struct mt7530_priv *priv = ds->priv; in mt7531_ind_phy_read()
795 int devad; in mt7531_ind_phy_read()
796 int ret; in mt7531_ind_phy_read()
809 static int
810 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, in mt7531_ind_phy_write()
813 struct mt7530_priv *priv = ds->priv; in mt7531_ind_phy_write()
814 int devad; in mt7531_ind_phy_write()
815 int ret; in mt7531_ind_phy_write()
830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, in mt7530_get_strings()
833 int i; in mt7530_get_strings()
844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, in mt7530_get_ethtool_stats()
847 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
857 if (mib->size == 2) { in mt7530_get_ethtool_stats()
864 static int
865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) in mt7530_get_sset_count()
875 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
877 int val; in mt7530_setup_port5()
879 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
886 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
888 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
892 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
899 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
906 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
907 priv->p5_intf_sel); in mt7530_setup_port5()
915 /* P5 RGMII RX Clock Control: delay setting for 1000M */ in mt7530_setup_port5()
919 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
924 /* P5 RGMII TX Clock Control: delay x */ in mt7530_setup_port5()
935 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
936 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
938 priv->p5_interface = interface; in mt7530_setup_port5()
941 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
944 static int
945 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) in mt753x_cpu_port_enable()
947 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
948 int ret; in mt753x_cpu_port_enable()
951 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
952 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
965 if (priv->id == ID_MT7621) in mt753x_cpu_port_enable()
972 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
977 static int
978 mt7530_port_enable(struct dsa_switch *ds, int port, in mt7530_port_enable()
981 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
986 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
992 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_enable()
993 priv->ports[port].enable = true; in mt7530_port_enable()
995 priv->ports[port].pm); in mt7530_port_enable()
998 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1004 mt7530_port_disable(struct dsa_switch *ds, int port) in mt7530_port_disable()
1006 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1011 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1016 priv->ports[port].enable = false; in mt7530_port_disable()
1021 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1025 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) in mt7530_stp_state_set()
1027 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1052 static int
1053 mt7530_port_bridge_join(struct dsa_switch *ds, int port, in mt7530_port_bridge_join()
1056 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1058 int i; in mt7530_port_bridge_join()
1060 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1068 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_join()
1070 if (priv->ports[i].enable) in mt7530_port_bridge_join()
1073 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1080 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1083 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1085 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1091 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_unaware()
1093 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1095 int i; in mt7530_port_set_vlan_unaware()
1098 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_set_vlan_unaware()
1120 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1127 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_aware()
1129 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1159 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, in mt7530_port_bridge_leave()
1162 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1163 int i; in mt7530_port_bridge_leave()
1165 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1171 * And the other port's port matrix cannot be broken when the in mt7530_port_bridge_leave()
1172 * other port is still a VLAN-aware port. in mt7530_port_bridge_leave()
1176 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_leave()
1178 if (priv->ports[i].enable) in mt7530_port_bridge_leave()
1181 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1188 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1191 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_bridge_leave()
1193 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1196 static int
1197 mt7530_port_fdb_add(struct dsa_switch *ds, int port, in mt7530_port_fdb_add()
1200 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1201 int ret; in mt7530_port_fdb_add()
1204 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1205 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1207 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1212 static int
1213 mt7530_port_fdb_del(struct dsa_switch *ds, int port, in mt7530_port_fdb_del()
1216 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1217 int ret; in mt7530_port_fdb_del()
1220 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1221 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1223 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1228 static int
1229 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, in mt7530_port_fdb_dump()
1232 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1234 int cnt = MT7530_NUM_FDB_RECORDS; in mt7530_port_fdb_dump()
1235 int ret = 0; in mt7530_port_fdb_dump()
1238 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1254 } while (--cnt && in mt7530_port_fdb_dump()
1258 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1263 static int
1268 int ret; in mt7530_vlan_cmd()
1277 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1283 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1284 return -EINVAL; in mt7530_vlan_cmd()
1290 static int
1291 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, in mt7530_port_vlan_filtering()
1299 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1302 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1313 static int
1314 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, in mt7530_port_vlan_prepare()
1329 new_members = entry->old_members | BIT(entry->port) | in mt7530_hw_vlan_add()
1341 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : in mt7530_hw_vlan_add()
1344 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1345 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1365 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1369 dev_err(priv->dev, in mt7530_hw_vlan_del()
1400 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1410 mt7530_port_vlan_add(struct dsa_switch *ds, int port, in mt7530_port_vlan_add()
1413 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1414 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1416 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1419 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1421 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in mt7530_port_vlan_add()
1429 G0_PORT_VID(vlan->vid_end)); in mt7530_port_vlan_add()
1430 priv->ports[port].pvid = vlan->vid_end; in mt7530_port_vlan_add()
1433 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1436 static int
1437 mt7530_port_vlan_del(struct dsa_switch *ds, int port, in mt7530_port_vlan_del()
1441 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1444 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1446 pvid = priv->ports[port].pvid; in mt7530_port_vlan_del()
1447 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in mt7530_port_vlan_del()
1460 priv->ports[port].pvid = pvid; in mt7530_port_vlan_del()
1462 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1467 static int mt753x_mirror_port_get(unsigned int id, u32 val) in mt753x_mirror_port_get()
1473 static int mt753x_mirror_port_set(unsigned int id, u32 val) in mt753x_mirror_port_set()
1479 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, in mt753x_port_mirror_add()
1483 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1484 int monitor_port; in mt753x_port_mirror_add()
1488 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1489 return -EEXIST; in mt753x_port_mirror_add()
1491 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1494 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1495 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1496 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1497 return -EEXIST; in mt753x_port_mirror_add()
1499 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1500 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1501 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1502 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1507 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1510 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1517 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, in mt753x_port_mirror_del()
1520 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1524 if (mirror->ingress) { in mt753x_port_mirror_del()
1526 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1529 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1533 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1534 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1535 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1536 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1541 mtk_get_tag_protocol(struct dsa_switch *ds, int port, in mtk_get_tag_protocol()
1544 struct mt7530_priv *priv = ds->priv; in mtk_get_tag_protocol()
1547 dev_warn(priv->dev, in mtk_get_tag_protocol()
1555 static int
1558 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
1565 int ret, i; in mt7530_setup()
1571 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; in mt7530_setup()
1572 ds->configure_vlan_while_not_filtering = true; in mt7530_setup()
1574 if (priv->id == ID_MT7530) { in mt7530_setup()
1575 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
1576 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
1578 dev_err(priv->dev, in mt7530_setup()
1583 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
1584 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
1586 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
1592 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
1595 if (priv->mcm) { in mt7530_setup()
1596 reset_control_assert(priv->rstc); in mt7530_setup()
1598 reset_control_deassert(priv->rstc); in mt7530_setup()
1600 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
1602 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
1605 /* Waiting for MT7530 got to stable */ in mt7530_setup()
1610 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
1617 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
1618 return -ENODEV; in mt7530_setup()
1632 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
1655 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
1659 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
1660 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
1661 if (ret && ret != -ENODEV) in mt7530_setup()
1667 "mediatek,eth-mac")) in mt7530_setup()
1674 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
1678 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
1680 if (ret && ret != -ENODEV) { in mt7530_setup()
1684 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
1686 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
1688 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
1706 static int
1709 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
1712 int ret, i; in mt7531_setup()
1714 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
1717 if (priv->mcm) { in mt7531_setup()
1718 reset_control_assert(priv->rstc); in mt7531_setup()
1720 reset_control_deassert(priv->rstc); in mt7531_setup()
1722 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
1724 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
1727 /* Waiting for MT7530 got to stable */ in mt7531_setup()
1732 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
1740 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
1741 return -ENODEV; in mt7531_setup()
1750 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
1752 /* Let ds->slave_mii_bus be able to access external phy. */ in mt7531_setup()
1758 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
1760 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
1761 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
1767 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
1768 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
1810 ds->configure_vlan_while_not_filtering = true; in mt7531_setup()
1821 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, in mt7530_phy_mode_supported()
1824 struct mt7530_priv *priv = ds->priv; in mt7530_phy_mode_supported()
1828 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
1832 if (!phy_interface_mode_is_rgmii(state->interface) && in mt7530_phy_mode_supported()
1833 state->interface != PHY_INTERFACE_MODE_MII && in mt7530_phy_mode_supported()
1834 state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
1838 if (state->interface != PHY_INTERFACE_MODE_RGMII && in mt7530_phy_mode_supported()
1839 state->interface != PHY_INTERFACE_MODE_TRGMII) in mt7530_phy_mode_supported()
1843 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7530_phy_mode_supported()
1853 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
1857 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, in mt7531_phy_mode_supported()
1860 struct mt7530_priv *priv = ds->priv; in mt7531_phy_mode_supported()
1864 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7531_phy_mode_supported()
1869 return phy_interface_mode_is_rgmii(state->interface); in mt7531_phy_mode_supported()
1872 if (state->interface != PHY_INTERFACE_MODE_SGMII && in mt7531_phy_mode_supported()
1873 !phy_interface_mode_is_8023z(state->interface)) in mt7531_phy_mode_supported()
1877 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7531_phy_mode_supported()
1886 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, in mt753x_phy_mode_supported()
1889 struct mt7530_priv *priv = ds->priv; in mt753x_phy_mode_supported()
1891 return priv->info->phy_mode_supported(ds, port, state); in mt753x_phy_mode_supported()
1894 static int
1897 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
1899 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
1902 static int
1903 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7530_mac_config()
1906 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
1912 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
1917 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, in mt7531_rgmii_setup()
1924 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
1926 return -EINVAL; in mt7531_rgmii_setup()
1956 return -EINVAL; in mt7531_rgmii_setup()
1964 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, in mt7531_sgmii_validate()
1983 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, in mt7531_sgmii_link_up_force()
1984 unsigned int mode, phy_interface_t interface, in mt7531_sgmii_link_up_force()
1985 int speed, int duplex) in mt7531_sgmii_link_up_force()
1987 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_link_up_force()
1988 unsigned int val; in mt7531_sgmii_link_up_force()
2026 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, in mt7531_sgmii_setup_mode_force()
2032 return -EINVAL; in mt7531_sgmii_setup_mode_force()
2039 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B in mt7531_sgmii_setup_mode_force()
2060 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, in mt7531_sgmii_setup_mode_an()
2064 return -EINVAL; in mt7531_sgmii_setup_mode_an()
2088 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) in mt7531_sgmii_restart_an()
2090 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_restart_an()
2101 static int
2102 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7531_mac_config()
2105 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2110 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2111 return -EINVAL; in mt7531_mac_config()
2120 phydev = dp->slave->phydev; in mt7531_mac_config()
2128 return -EINVAL; in mt7531_mac_config()
2132 return -EINVAL; in mt7531_mac_config()
2135 return -EINVAL; in mt7531_mac_config()
2138 static int
2139 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_mac_config()
2142 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2144 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2148 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_phylink_mac_config()
2151 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2159 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt753x_phylink_mac_config()
2163 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2169 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2170 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
2173 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
2181 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
2185 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
2186 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
2191 state->interface != PHY_INTERFACE_MODE_SGMII) { in mt753x_phylink_mac_config()
2192 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in mt753x_phylink_mac_config()
2201 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
2212 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) in mt753x_phylink_mac_an_restart()
2214 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_an_restart()
2216 if (!priv->info->mac_pcs_an_restart) in mt753x_phylink_mac_an_restart()
2219 priv->info->mac_pcs_an_restart(ds, port); in mt753x_phylink_mac_an_restart()
2222 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_down()
2223 unsigned int mode, in mt753x_phylink_mac_link_down()
2226 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
2231 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, in mt753x_mac_pcs_link_up()
2232 unsigned int mode, phy_interface_t interface, in mt753x_mac_pcs_link_up()
2233 int speed, int duplex) in mt753x_mac_pcs_link_up()
2235 struct mt7530_priv *priv = ds->priv; in mt753x_mac_pcs_link_up()
2237 if (!priv->info->mac_pcs_link_up) in mt753x_mac_pcs_link_up()
2240 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); in mt753x_mac_pcs_link_up()
2243 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_up()
2244 unsigned int mode, in mt753x_phylink_mac_link_up()
2247 int speed, int duplex, in mt753x_phylink_mac_link_up()
2250 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
2257 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
2285 static int
2286 mt7531_cpu_port_config(struct dsa_switch *ds, int port) in mt7531_cpu_port_config()
2288 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
2290 int speed; in mt7531_cpu_port_config()
2291 int ret; in mt7531_cpu_port_config()
2300 priv->p5_interface = interface; in mt7531_cpu_port_config()
2307 priv->p6_interface = interface; in mt7531_cpu_port_config()
2310 return -EINVAL; in mt7531_cpu_port_config()
2322 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
2330 mt7530_mac_port_validate(struct dsa_switch *ds, int port, in mt7530_mac_port_validate()
2337 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, in mt7531_mac_port_validate()
2340 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_validate()
2346 mt753x_phylink_validate(struct dsa_switch *ds, int port, in mt753x_phylink_validate()
2351 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_validate()
2353 if (state->interface != PHY_INTERFACE_MODE_NA && in mt753x_phylink_validate()
2361 if (state->interface != PHY_INTERFACE_MODE_TRGMII || in mt753x_phylink_validate()
2362 !phy_interface_mode_is_8023z(state->interface)) { in mt753x_phylink_validate()
2370 /* This switch only supports 1G full-duplex. */ in mt753x_phylink_validate()
2371 if (state->interface != PHY_INTERFACE_MODE_MII) in mt753x_phylink_validate()
2374 priv->info->mac_port_validate(ds, port, mask); in mt753x_phylink_validate()
2380 linkmode_and(state->advertising, state->advertising, mask); in mt753x_phylink_validate()
2388 static int
2389 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt7530_phylink_mac_link_state()
2392 struct mt7530_priv *priv = ds->priv; in mt7530_phylink_mac_link_state()
2396 return -EINVAL; in mt7530_phylink_mac_link_state()
2400 state->link = (pmsr & PMSR_LINK); in mt7530_phylink_mac_link_state()
2401 state->an_complete = state->link; in mt7530_phylink_mac_link_state()
2402 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_phylink_mac_link_state()
2406 state->speed = SPEED_10; in mt7530_phylink_mac_link_state()
2409 state->speed = SPEED_100; in mt7530_phylink_mac_link_state()
2412 state->speed = SPEED_1000; in mt7530_phylink_mac_link_state()
2415 state->speed = SPEED_UNKNOWN; in mt7530_phylink_mac_link_state()
2419 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_phylink_mac_link_state()
2421 state->pause |= MLO_PAUSE_RX; in mt7530_phylink_mac_link_state()
2423 state->pause |= MLO_PAUSE_TX; in mt7530_phylink_mac_link_state()
2428 static int
2429 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, in mt7531_sgmii_pcs_get_state_an()
2436 state->link = !!(status & MT7531_SGMII_LINK_STATUS); in mt7531_sgmii_pcs_get_state_an()
2437 if (state->interface == PHY_INTERFACE_MODE_SGMII && in mt7531_sgmii_pcs_get_state_an()
2444 state->speed = SPEED_1000; in mt7531_sgmii_pcs_get_state_an()
2447 state->speed = SPEED_100; in mt7531_sgmii_pcs_get_state_an()
2450 state->speed = SPEED_10; in mt7531_sgmii_pcs_get_state_an()
2453 dev_err(priv->dev, "invalid sgmii PHY speed\n"); in mt7531_sgmii_pcs_get_state_an()
2454 state->link = false; in mt7531_sgmii_pcs_get_state_an()
2455 return -EINVAL; in mt7531_sgmii_pcs_get_state_an()
2459 state->duplex = DUPLEX_FULL; in mt7531_sgmii_pcs_get_state_an()
2461 state->duplex = DUPLEX_HALF; in mt7531_sgmii_pcs_get_state_an()
2467 static int
2468 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt7531_phylink_mac_link_state()
2471 struct mt7530_priv *priv = ds->priv; in mt7531_phylink_mac_link_state()
2473 if (state->interface == PHY_INTERFACE_MODE_SGMII) in mt7531_phylink_mac_link_state()
2476 return -EOPNOTSUPP; in mt7531_phylink_mac_link_state()
2479 static int
2480 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_state()
2483 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_state()
2485 return priv->info->mac_port_get_state(ds, port, state); in mt753x_phylink_mac_link_state()
2488 static int
2491 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
2493 return priv->info->sw_setup(ds); in mt753x_setup()
2496 static int
2497 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) in mt753x_phy_read()
2499 struct mt7530_priv *priv = ds->priv; in mt753x_phy_read()
2501 return priv->info->phy_read(ds, port, regnum); in mt753x_phy_read()
2504 static int
2505 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) in mt753x_phy_write()
2507 struct mt7530_priv *priv = ds->priv; in mt753x_phy_write()
2509 return priv->info->phy_write(ds, port, regnum, val); in mt753x_phy_write()
2589 static int
2595 dn = mdiodev->dev.of_node; in mt7530_probe()
2597 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in mt7530_probe()
2599 return -ENOMEM; in mt7530_probe()
2601 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe()
2602 if (!priv->ds) in mt7530_probe()
2603 return -ENOMEM; in mt7530_probe()
2605 priv->ds->dev = &mdiodev->dev; in mt7530_probe()
2606 priv->ds->num_ports = DSA_MAX_PORTS; in mt7530_probe()
2609 * casues a little bit differences on power-on sequence. in mt7530_probe()
2611 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); in mt7530_probe()
2612 if (priv->mcm) { in mt7530_probe()
2613 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); in mt7530_probe()
2615 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); in mt7530_probe()
2616 if (IS_ERR(priv->rstc)) { in mt7530_probe()
2617 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
2618 return PTR_ERR(priv->rstc); in mt7530_probe()
2623 * We will need it for some of the clock and regulator setup. in mt7530_probe()
2625 priv->info = of_device_get_match_data(&mdiodev->dev); in mt7530_probe()
2626 if (!priv->info) in mt7530_probe()
2627 return -EINVAL; in mt7530_probe()
2632 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe()
2633 !priv->info->phy_read || !priv->info->phy_write || in mt7530_probe()
2634 !priv->info->phy_mode_supported || in mt7530_probe()
2635 !priv->info->mac_port_validate || in mt7530_probe()
2636 !priv->info->mac_port_get_state || !priv->info->mac_port_config) in mt7530_probe()
2637 return -EINVAL; in mt7530_probe()
2639 priv->id = priv->info->id; in mt7530_probe()
2641 if (priv->id == ID_MT7530) { in mt7530_probe()
2642 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); in mt7530_probe()
2643 if (IS_ERR(priv->core_pwr)) in mt7530_probe()
2644 return PTR_ERR(priv->core_pwr); in mt7530_probe()
2646 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); in mt7530_probe()
2647 if (IS_ERR(priv->io_pwr)) in mt7530_probe()
2648 return PTR_ERR(priv->io_pwr); in mt7530_probe()
2653 * the reset, otherwise memory-mapped register accessing used in mt7530_probe()
2656 if (!priv->mcm) { in mt7530_probe()
2657 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", in mt7530_probe()
2659 if (IS_ERR(priv->reset)) { in mt7530_probe()
2660 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
2661 return PTR_ERR(priv->reset); in mt7530_probe()
2665 priv->bus = mdiodev->bus; in mt7530_probe()
2666 priv->dev = &mdiodev->dev; in mt7530_probe()
2667 priv->ds->priv = priv; in mt7530_probe()
2668 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe()
2669 mutex_init(&priv->reg_mutex); in mt7530_probe()
2670 dev_set_drvdata(&mdiodev->dev, priv); in mt7530_probe()
2672 return dsa_register_switch(priv->ds); in mt7530_probe()
2678 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); in mt7530_remove()
2679 int ret = 0; in mt7530_remove()
2681 ret = regulator_disable(priv->core_pwr); in mt7530_remove()
2683 dev_err(priv->dev, in mt7530_remove()
2686 ret = regulator_disable(priv->io_pwr); in mt7530_remove()
2688 dev_err(priv->dev, "Failed to disable io pwr: %d\n", in mt7530_remove()
2691 dsa_unregister_switch(priv->ds); in mt7530_remove()
2692 mutex_destroy(&priv->reg_mutex); in mt7530_remove()